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1.1. JESD204B Design Example Quick Start Guide
1.2. Supported Configurations
1.3. Generic Design Example
1.4. Presets
1.5. Selecting and Generating the Design Example
1.6. Design Example with RTL State Machine Control Unit
1.7. Design Example with NIOS Control Unit
1.8. JESD204B Intel® FPGA IP Design Example User Guide Document Archives
1.9. Document Revision History for the JESD204B Intel® FPGA IP Design Example User Guide
1.7.1. Design Example Components
1.7.2. System Clocking
1.7.3. Nios II Processor Design Example Files
1.7.4. Nios II Processor Design Example System Parameters
1.7.5. Nios II Processor Design Example System Interface Signals
1.7.6. Compiling the Design Example for Synthesis
1.7.7. Implementing the Design on the Development Kit
1.7.8. Running the Software Control Flow
1.7.9. Customizing the Design Example
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1.6.5. Generating and Simulating the Design Example
To use the JESD204B IP core design example testbench, follow these steps:
- Generate the design example simulation testbench. Refer to Generating the Design Example Simulation Model
- Simulate the design example using simulator-specific scripts. Refer to Simulating the JESD204B IP Core Design Example
Section Content
Generating the Design Example Simulation Model
Simulating the JESD204B IP Core Design Example
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