JESD204B Intel® FPGA IP Design Example User Guide: Intel® Quartus® Prime Standard Edition

ID 683094
Date 10/31/2022
Document Table of Contents

1.6.1. Design Example Components

The RTL State Machine Control Unit design example for the JESD204B IP core consists of the following components:

  • PLL
  • PLL reconfiguration
  • Transceiver reconfiguration controller
  • Transceiver reset controller
  • Pattern generator
  • Pattern checker
  • Assembler and deassembler (in the transport layer)
  • SPI
  • Control unit

The following sections describe in detail the function of each component.