JESD204B Intel® FPGA IP Design Example User Guide: Intel® Quartus® Prime Standard Edition

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Date 10/31/2022
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® FPGA IP Design Example User Guide
1. JESD204B Intel® FPGA IP Design Example User Guide x
1.1. JESD204B Design Example Quick Start Guide 1.2. Supported Configurations 1.3. Generic Design Example 1.4. Presets 1.5. Selecting and Generating the Design Example 1.6. Design Example with RTL State Machine Control Unit 1.7. Design Example with NIOS Control Unit 1.8. JESD204B Intel® FPGA IP Design Example User Guide Document Archives 1.9. Document Revision History for the JESD204B Intel® FPGA IP Design Example User Guide
1.1. JESD204B Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Compiling and Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Procedure 1.1.2.2. Design Example Parameters
1.1.3. Compiling and Simulating the Design x
1.1.3.1. Procedure
1.6. Design Example with RTL State Machine Control Unit x
1.6.1. Design Example Components 1.6.2. System Parameters 1.6.3. System Interface Signals 1.6.4. Example Feature: Dynamic Reconfiguration 1.6.5. Generating and Simulating the Design Example 1.6.6. Generating the Design Example For Compilation 1.6.7. Compiling the JESD204B IP Core Design Example
1.6.1. Design Example Components x
1.6.1.1. PLL 1.6.1.2. PLL Reconfiguration 1.6.1.3. Transceiver Reconfiguration Controller 1.6.1.4. Transceiver Reset Controller 1.6.1.5. Pattern Generator 1.6.1.6. Pattern Checker 1.6.1.7. Transport Layer 1.6.1.8. Serial Port Interface (SPI) 1.6.1.9. Control Unit
1.6.1.5. Pattern Generator x
1.6.1.5.1. Parallel PRBS Generator 1.6.1.5.2. Alternate Checkerboard Generator 1.6.1.5.3. Ramp Wave Generator
1.6.1.6. Pattern Checker x
1.6.1.6.1. Parallel PRBS Checker 1.6.1.6.2. Alternate Checkerboard Checker 1.6.1.6.3. Ramp Wave Checker
1.6.1.7. Transport Layer x
1.6.1.7.1. Supported System Configuration 1.6.1.7.2. Data Bit and Content Mapping Scheme 1.6.1.7.3. TX Path 1.6.1.7.4. RX Path
1.6.1.9. Control Unit x
1.6.1.9.1. Memory Block (ROM) 1.6.1.9.2. Finite State Machine (FSM)
1.6.2. System Parameters x
1.6.2.1. Run-Time Reconfiguration
1.6.4. Example Feature: Dynamic Reconfiguration x
1.6.4.1. Dynamic Reconfiguration Operation 1.6.4.2. MIF ROM Core PLL PHY (Stratix V and Arria V) PHY (Arria 10) JESD ADC/DAC/CLK
1.6.5. Generating and Simulating the Design Example x
1.6.5.1. Generating the Design Example Simulation Model 1.6.5.2. Simulating the JESD204B IP Core Design Example
1.7. Design Example with NIOS Control Unit x
1.7.1. Design Example Components 1.7.2. System Clocking 1.7.3. Nios II Processor Design Example Files 1.7.4. Nios II Processor Design Example System Parameters 1.7.5. Nios II Processor Design Example System Interface Signals 1.7.6. Compiling the Design Example for Synthesis 1.7.7. Implementing the Design on the Development Kit 1.7.8. Running the Software Control Flow 1.7.9. Customizing the Design Example
1.7.1. Design Example Components x
1.7.1.1. Platform Designer (Standard) System Component 1.7.1.2. Transport Layer 1.7.1.3. Test Pattern Generator 1.7.1.4. Test Pattern Checker
1.7.1.1. Platform Designer (Standard) System Component x
1.7.1.1.1. JESD204B Subsystem in Platform Designer (Standard) 1.7.1.1.2. Nios II Subsystem in Platform Designer (Standard) 1.7.1.1.3. Core PLL 1.7.1.1.4. PLL Reconfiguration Controller 1.7.1.1.5. SPI Master
1.7.7. Implementing the Design on the Development Kit x
1.7.7.1. Pin Assignments 1.7.7.2. Hardware Setup 1.7.7.3. Programming the Device
1.7.8. Running the Software Control Flow x
1.7.8.1. Executing the Software C Code 1.7.8.2. Software Parameters 1.7.8.3. Software Interrupt Service Routines (ISR) 1.7.8.4. Software Functions Description
1.7.8.4. Software Functions Description x
1.7.8.4.1. Functions in main.c Source File 1.7.8.4.2. Custom Peripheral Access Macros in macros.c Source File
1.7.9. Customizing the Design Example x
1.7.9.1. Modifying the JESD204B IP Core Parameters Post-Generation 1.7.9.2. Changing the Data Rate or Reference Clock Frequency 1.7.9.3. Implementing a Multi-Link Design
1.7.9.3. Implementing a Multi-Link Design x
1.7.9.3.1. Editing the Platform Designer (Standard) Project 1.7.9.3.2. Editing the Top Level HDL File 1.7.9.3.3. Editing the Software C Code
1. JESD204B Intel® FPGA IP Design Example User Guide

1.6.4.2. MIF ROM

You need to generate two MIF files for each reconfigurable IP core as shown in Dynamic Reconfiguration Operation, and merge them into a single MIF file for each IP core. The following section shows the MIF file format.

Core PLL

The MIF format is fixed by the PLL. You need to generate two PLLs with maximum and downscale setting to get these two MIF files. Then, merge the files into one (core_pll.mif). Only the PLL with maximum configuration is used in final compilation. 

Maximum Configuration MIF
WIDTH=32;
DEPTH=92;

ADDRESS_RADIX=UNS;
DATA_RADIX=BIN;

CONTENT BEGIN
	0   :   00000000000000000000000000111110; -- START OF MIF
	1   :   00000000000000000000000000000100;
	2   :   00000000000000000000000100000001;
	3   :   00000000000000000000000000000011;
.
.
.
 42  :   00000000000000000000000000000010;
	43  :   00000000000000000000000000001000;
	44  :   00000000000000000000000001000000;
	45  :   00000000000000000000000000111111; -- END OF MIF

Downscale Configuration MIF

 46  :   00000000000000000000000000111110; -- START OF MIF
	47  :   00000000000000000000000000000100;
	48  :   00000000000000000000000100000001;
	49  :   00000000000000000000000000000011;
.
.
.
 88  :   00000000000000000000000000000010;
	89  :   00000000000000000000000000001000;
	90  :   00000000000000000000000001000000;
	91  :   00000000000000000000000000111111; -- END OF MIF
END;

PHY (Stratix V and Arria V)

The MIF format is fixed by the PHY. You need to generate two JESD204B IP cores with maximum and downscale setting. Then, compile each of the setting to get a total of four MIF files (two for TX PLL and two for channel MIF). Then, merge the files into one (phy.mif). Only the JESD204B IP cores with maximum configuration is used in final compilation. 

Maximum TX PLL Configuration MIF
WIDTH=16;
DEPTH=186;

ADDRESS_RADIX=UNS;
DATA_RADIX=BIN;

CONTENT BEGIN
	0    :   0000000000100001; -- Start of MIF opcode (TX_PLL, 6144Mbps)
	1    :   0000000000100010;
.
.
.
 10   :   0011000000000000;
	11   :   0000000000011111; -- End of MIF opcode

Maximum Channel Configuration MIF

 12   :   0000000000100001; -- Start of MIF opcode (Channel, 6144Mbps)
	13   :   0000000000000010;
.
.
.
 [88..91]  :   0000000000000000;
	92   :   0000000000011111; -- End of MIF opcode

Downscale TX PLL Configuration MIF

 93   :   0000000000100001; -- Start of MIF opcode (TX_PLL, 3072Mbps)
	94   :   0000000000100010;
.
.
.
 103  :   0011000000000000;
	104  :   0000000000011111; -- End of MIF opcode

Downscale Channel Configuration MIF

 105  :   0000000000100001; -- Start of MIF opcode (Channel, 3072Mbps)
	106  :   0000000000000010;
.
.
.
 [181..184]  :   0000000000000000;
	185  :   0000000000011111; -- End of MIF opcode
END;

PHY (Arria 10)

The MIF format is fixed by the PHY. You need to generate two JESD204B IP cores with maximum and downscale setting. Then, compile each of the setting to get a total of four MIF files (two for TX PLL and two for channel MIF). Then, merge the files into two (xcvr_atx_pll_combined.mif and xcvr_cdr_combined.mif). Only the JESD204B IP cores with maximum configuration is used in final compilation. 

xcvr_atx_pll_combined.mif

Maximum Configuration MIF

CONTENT BEGIN
	00    :   102FF71; -- Start of MIF
	01    :   103BF01;
	02    :   1047F04;
	03    :   1054700;
.
.
.
 10   :   11AFF00;
	11   :   11CE020;
	12   :   11DE020;
	13   :   3FFFFFF; -- End of MIF

Downscale Channel Configuration MIF

	14    :   102FF71; -- Start of MIF
	15    :   103BF01;
	16    :   1047F04;
	17    :   1054700;
.
.
.
 24   :   11AFF00;
	25   :   11CE020;
	26   :   11DE020;
	27   :   3FFFFFF; -- End of MIF
END;

xcvr_cdr_combined.mif

Maximum Configuration MIF

CONTENT BEGIN
	00    :   006DF02; -- Start of MIF
	01    :   007FF09;
	02    :   008FF04;
	03    :   00AFF01;
.
.
.
 76   :   173FF31;
	77   :   1741F0C;
	78   :   1753F13;
	79   :   3FFFFFF; -- End of MIF

Downscale Channel Configuration MIF

	7A    :   006DF02; -- Start of MIF
	7B    :   007FF09;
	7C    :   008FF04;
	7D    :   00AFF01;
.
.
.
 F0   :   173FF31;
	F1   :   1741F0C;
	F2   :   1753F13;
	F3   :   3FFFFFF; -- End of MIF
END;

JESD

The current JESD MIF contains only the LMF information. You need to manually code the MIF content in the following format. 

Maximum Configuration MIF
WIDTH=16;
DEPTH=16;

ADDRESS_RADIX=UNS;
DATA_RADIX=BIN;

CONTENT BEGIN
	0    :   0000000000000001; -- L            (maximum config)
	1    :   0000000000000001; -- M
	2    :   0000000000000001; -- F
.
.
.
 3    :   1111111111111111; -- End of MIF
 [4..7]  :   0000000000000000; 

Downscale Configuration MIF

 8    :   0000000000000000; -- L            (downscale config)
 9    :   0000000000000000; -- M
 10   :   0000000000000001; -- F
.
.
.
 11   :   1111111111111111; -- End of MIF
 [12..15]  :   0000000000000000; 
END;

ADC/DAC/CLK

The content for ADC/DAC/CLK MIF is vendor-specific. The general format for the MIF is as shown below, with each section terminated by all 1's. 

Maximum Configuration MIF
WIDTH=32;
DEPTH=128;

ADDRESS_RADIX=UNS;
DATA_RADIX=BIN;

CONTENT BEGIN
	0   :   10000100000000000001000001111100;  -- (Maximum Config)
	1   :   10000100000000000001010000000101;  
	2   :   10000100000000000001011000000101;  
	3   :   10000100000000000001110000000010;  
.
.
.
 28  :   10000001000000001111111100000001;  
	29  :   10000001000000000101111100010100;  
	30  :   11111111111111111111111111111111;  -- End of MIF
	[31..63] :   00000000000000000000000000000000;

Downscale Configuration MIF

 64  :   10000100000000000001000001111100;   -- (downscale config)
 65  :   10000100000000000001010000000101;
 66  :   10000100000000000001011000000101;
 67  :   10000100000000000001110000000010;
.
.
.
 92  :   10000001000000001111111100000001; 
 93  :   10000001000000000101111100010100;
 94  :   11111111111111111111111111111111;  -- End of MIF
 95..127]  :   00000000000000000000000000000000;
END;
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