JESD204B Intel® FPGA IP Design Example User Guide: Intel® Quartus® Prime Standard Edition

ID 683094
Date 10/31/2022
Document Table of Contents Transceiver Reconfiguration Controller

The transceiver reconfiguration controller allows you to change the device transceiver settings at any time. Any portion of the transceiver can be selectively reconfigured. Each portion of the reconfiguration requires a read-modify-write operation (read first, then write), in such a way that it modifies only the appropriate bits in a register and not changing other bits.

In the design example, MIF approach is used to reconfigure the ATX PLL and transceiver channel in the JESD204 IP core via the Transceiver Reconfiguration Controller. The number of reconfiguration interface is determined by number of lanes (L) + number of TX_PLL (different number of TX_PLL for bonded and non-bonded mode). Since the MIF approach reconfiguration for transceiver only supports non-bonded mode, the number of TX_PLL is equal to number of lanes. The number of reconfiguration interface = 2 x number of lanes (L).

The transceiver reconfiguration controller interfaces:

  • MIF Reconfiguration Avalon-MM master interface—connects to the MIF ROM.
  • Transceiver Reconfiguration interface—connects to the JESD204B IP core, which eventually connects to the native PHY.
  • Reconfiguration Management Avalon-MM slave interface—connects to the control unit.
Note: The transceiver reconfiguration controller is only used in Arria V and Stratix V devices. For Arria 10 devices, the control unit directly communicates with the transceiver in the JESD204B IP core through the reconfig_avmm_* interface signals.

The following transceiver reconfiguration controller Avalon-MM operations are involved during data rate reconfiguration.

Table 10.   Transceiver Reconfiguration Controller Operation for Arria V and Stratix V Devices
Operation Avalon-MM Interface Signal Byte Address Offset (6bits) Bit Value
Write logical channel number reconfig_mgmt_* 0x38 [9:0] 0
Write MIF mode reconfig_mgmt_* 0x3A [3:2] 2'b00
Write 0 to streamer offset register reconfig_mgmt_* 0x3B [15:0] 0
Write MIF base address to streamer data register reconfig_mgmt_* 0X3C [31:0] *32'h1000
Initiate a write of all the above data reconfig_mgmt_* 0x3A [0] 1'b1
Write 1 to streamer offset register reconfig_mgmt_* 0x3B [15:0] 1
Write to streamer data register to set up MIF streaming reconfig_mgmt_* 0x3C [31:0] 3
Initiate a write of all the above data to start streaming the MIF reconfig_mgmt_* 0x3A [0] 1'b1
Read the busy bit to determine when the write has completed reconfig_mgmt_* 0x3A [8]

1: Busy

0: Operation completed

Note: The above steps are repeated for the number of channels and followed by the number of TX_PLLs.

For Arria 10 devices, the only Avalon-MM operation is a direct write to the transceiver register through the reconfig_avmm_* interface at the JESD204B IP core. Every line in the MIF is DPRIO_ADDR[25:16]+ BIT_MASK[15:8]+ DATA[7:0]. The control unit maps the DPRIO_ADDR to reconfig_avmm_address and BIT_MASK + DATA to reconfig_avmm_data.