JESD204B Intel® FPGA IP Design Example User Guide: Intel® Quartus® Prime Standard Edition

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ID 683094
Date 10/31/2022
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® FPGA IP Design Example User Guide
1. JESD204B Intel® FPGA IP Design Example User Guide x
1.1. JESD204B Design Example Quick Start Guide 1.2. Supported Configurations 1.3. Generic Design Example 1.4. Presets 1.5. Selecting and Generating the Design Example 1.6. Design Example with RTL State Machine Control Unit 1.7. Design Example with NIOS Control Unit 1.8. JESD204B Intel® FPGA IP Design Example User Guide Document Archives 1.9. Document Revision History for the JESD204B Intel® FPGA IP Design Example User Guide
1.1. JESD204B Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Compiling and Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Procedure 1.1.2.2. Design Example Parameters
1.1.3. Compiling and Simulating the Design x
1.1.3.1. Procedure
1.6. Design Example with RTL State Machine Control Unit x
1.6.1. Design Example Components 1.6.2. System Parameters 1.6.3. System Interface Signals 1.6.4. Example Feature: Dynamic Reconfiguration 1.6.5. Generating and Simulating the Design Example 1.6.6. Generating the Design Example For Compilation 1.6.7. Compiling the JESD204B IP Core Design Example
1.6.1. Design Example Components x
1.6.1.1. PLL 1.6.1.2. PLL Reconfiguration 1.6.1.3. Transceiver Reconfiguration Controller 1.6.1.4. Transceiver Reset Controller 1.6.1.5. Pattern Generator 1.6.1.6. Pattern Checker 1.6.1.7. Transport Layer 1.6.1.8. Serial Port Interface (SPI) 1.6.1.9. Control Unit
1.6.1.5. Pattern Generator x
1.6.1.5.1. Parallel PRBS Generator 1.6.1.5.2. Alternate Checkerboard Generator 1.6.1.5.3. Ramp Wave Generator
1.6.1.6. Pattern Checker x
1.6.1.6.1. Parallel PRBS Checker 1.6.1.6.2. Alternate Checkerboard Checker 1.6.1.6.3. Ramp Wave Checker
1.6.1.7. Transport Layer x
1.6.1.7.1. Supported System Configuration 1.6.1.7.2. Data Bit and Content Mapping Scheme 1.6.1.7.3. TX Path 1.6.1.7.4. RX Path
1.6.1.9. Control Unit x
1.6.1.9.1. Memory Block (ROM) 1.6.1.9.2. Finite State Machine (FSM)
1.6.2. System Parameters x
1.6.2.1. Run-Time Reconfiguration
1.6.4. Example Feature: Dynamic Reconfiguration x
1.6.4.1. Dynamic Reconfiguration Operation 1.6.4.2. MIF ROM
1.6.5. Generating and Simulating the Design Example x
1.6.5.1. Generating the Design Example Simulation Model 1.6.5.2. Simulating the JESD204B IP Core Design Example
1.7. Design Example with NIOS Control Unit x
1.7.1. Design Example Components 1.7.2. System Clocking 1.7.3. Nios II Processor Design Example Files 1.7.4. Nios II Processor Design Example System Parameters 1.7.5. Nios II Processor Design Example System Interface Signals 1.7.6. Compiling the Design Example for Synthesis 1.7.7. Implementing the Design on the Development Kit 1.7.8. Running the Software Control Flow 1.7.9. Customizing the Design Example
1.7.1. Design Example Components x
1.7.1.1. Platform Designer (Standard) System Component 1.7.1.2. Transport Layer 1.7.1.3. Test Pattern Generator 1.7.1.4. Test Pattern Checker
1.7.1.1. Platform Designer (Standard) System Component x
1.7.1.1.1. JESD204B Subsystem in Platform Designer (Standard) 1.7.1.1.2. Nios II Subsystem in Platform Designer (Standard) 1.7.1.1.3. Core PLL 1.7.1.1.4. PLL Reconfiguration Controller 1.7.1.1.5. SPI Master
1.7.7. Implementing the Design on the Development Kit x
1.7.7.1. Pin Assignments 1.7.7.2. Hardware Setup 1.7.7.3. Programming the Device
1.7.8. Running the Software Control Flow x
1.7.8.1. Executing the Software C Code 1.7.8.2. Software Parameters 1.7.8.3. Software Interrupt Service Routines (ISR) 1.7.8.4. Software Functions Description
1.7.8.4. Software Functions Description x
1.7.8.4.1. Functions in main.c Source File 1.7.8.4.2. Custom Peripheral Access Macros in macros.c Source File
1.7.9. Customizing the Design Example x
1.7.9.1. Modifying the JESD204B IP Core Parameters Post-Generation 1.7.9.2. Changing the Data Rate or Reference Clock Frequency 1.7.9.3. Implementing a Multi-Link Design
1.7.9.3. Implementing a Multi-Link Design x
1.7.9.3.1. Editing the Platform Designer (Standard) Project 1.7.9.3.2. Editing the Top Level HDL File 1.7.9.3.3. Editing the Software C Code
1. JESD204B Intel® FPGA IP Design Example User Guide

1.7.1.1. Platform Designer (Standard) System Component

The Platform Designer (Standard) system instantiates both the JESD204B IP core data path and the Nios II subsystem control path.

Figure 25. Platform Designer (Standard) System


The top level Platform Designer (Standard) system, jesd204b_ed_qsys.qsys, instantiates the following modules:

  • JESD204B subsystem
  • Nios II subsystem
  • Core PLL
  • PLL reconfiguration controller
  • SPI master

The main data path flows through the JESD204B subsystem. In the example design, the JESD204B IP core is configured in duplex mode with both TX and RX data paths. On the TX data path, user data flows from the transport layer through the JESD204B IP core base module via a 32-bit per transceiver lane Avalon Streaming (Avalon-ST) interface and out as serial data to the external converters via the JESD204B IP core PHY module. On the RX data path, serial data flows from the external converters (or from the TX data path, in internal serial loopback mode) to the JESD204B IP core PHY module and out from the JESD204B IP core base module to the transport layer via a 32-bit per transceiver lane Avalon-ST interface.

The control path is centered on the Nios II processor in the Nios II subsystem and connects to various peripherals via the Avalon Memory-Mapped (Avalon-MM) interface. A secondary control path from the SPI master module links out to the SPI configuration interface of external converters via a 4-wire SPI interconnect. The configuration of the external converters is done by writing configuration data from the Nios II processor to the SPI master module. The SPI master module handles the serial transfer of data to the SPI interface on the converter end via the 4-wire SPI interconnect.

The core PLL generates the link clock and frame clock for the system. During a data rate dynamic reconfiguration process, the core PLL is dynamically reconfigurable at run time via the PLL reconfiguration controller.

To view the top level Platform Designer (Standard) system in Platform Designer (Standard), follow these steps:

  1. Launch the Intel® Quartus® Prime software.
  2. On the File menu, click Open.
  3. Browse and select the jesd204b_ed_qsys.qsys file located in the project directory.
  4. Click Open to view the Platform Designer (Standard) system.

You can access the address mapping of the submodules in the top level Platform Designer (Standard) project by clicking on the Address Map tab in the Platform Designer (Standard) window.

Figure 26. Address Map View in Platform Designer (Standard)


The Platform Designer (Standard) system supports multi-link scenarios (up to 16 links) using the existing address map. To add more links to the system, add more jesd204b_subsystem.qsys modules to the project, connect them to the jesd204b_subsystem Avalon-MM bridge, and adjust the address map accordingly. Bits 16-19 of the nios_subsystem-to-jesd204b_subsystem Avalon-MM bridge are reserved to support multi-links.


Section Content
JESD204B Subsystem in Platform Designer (Standard)
Nios II Subsystem in Platform Designer (Standard)
Core PLL
PLL Reconfiguration Controller
SPI Master

Level Two Title