JESD204B Intel® FPGA IP Design Example User Guide: Intel® Quartus® Prime Standard Edition

ID 683094
Date 10/31/2022
Document Table of Contents Core PLL

The core PLL is an Arria 10 I/O PLL (altera_iopll) module that generates the clocks for the FPGA core fabric.
The core PLL uses the device_clk as its reference clock to generate two derivative clocks from a single VCO:
  • Link clock – from output C0
  • Frame clock – from output C1
Table 38.  Clocks
Clock Formula Description
Link Clock Serial data rate/40 The link clock clocks the JESD204B IP core link layer and the link interface of the transport layer.
Frame Clock Serial data rate/(10 × F) The frame clock clocks the transport layer, test pattern generators and checkers, and any downstream modules in the FPGA core fabric.

For the frame clock, when F=1 and F=2, the resulting frame clock value can easily exceed the capability of the core PLL to generate and close timing. The top level RTL file ( defines the frame clock division factor parameters, F1_FRAMECLK_DIV (for cases with F = 1) and F2_FRAMECLK_DIV (for cases with F = 2). This factor enables the transport layer and test pattern generator to operate at a divided factor of the required frame clock rate by widening the data width accordingly. For this example design, the F1_FRAMECLK_DIV is set to 4 and F2_FRAMECLK_DIV is set to 2. For example, the actual frame clock for a serial data rate of 6.144 Gbps and F = 1 is:

(6144/(10 × 1)) / F1_FRAMECLK_DIV = 614.4 / 4 = 153.6 MHz

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