JESD204B Intel® FPGA IP Design Example User Guide: Intel® Quartus® Prime Standard Edition

ID 683094
Date 10/31/2022

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Document Table of Contents Editing the Top Level HDL File

  1. Open the top level HDL file ( in any text editor.
  2. Modify the LINK system parameter to reflect the number of links in your design.
  3. Replace the single-link jesd204b_ed_qsys instance with the multi-link instance generated earlier as shown in Editing the Platform Designer (Standard) Project.
  4. Reconnect all the ports that are similar between the single-link jesd204b_ed_qsys instance and the multi-link instance.
  5. The ports that are new in the multi-link jesd204b_ed_qsys instance are associated with the jesd204b_subsystem_1 module. Connect the ports that have the jesd204b_subsystem_1_* prefix in the same manner as shown below:
  6. Save the file and compile the design in the Intel® Quartus® Prime software.

Ensure that any additional pins that are created from the addition of multi-links (for example, tx_serial_data and rx_serial_data pins) have proper pin assignments in the Quartus settings file (jesd204b_ed.qsf).