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1.1. JESD204B Design Example Quick Start Guide
1.2. Supported Configurations
1.3. Generic Design Example
1.4. Presets
1.5. Selecting and Generating the Design Example
1.6. Design Example with RTL State Machine Control Unit
1.7. Design Example with NIOS Control Unit
1.8. JESD204B Intel® FPGA IP Design Example User Guide Document Archives
1.9. Document Revision History for the JESD204B Intel® FPGA IP Design Example User Guide
1.7.1. Design Example Components
1.7.2. System Clocking
1.7.3. Nios II Processor Design Example Files
1.7.4. Nios II Processor Design Example System Parameters
1.7.5. Nios II Processor Design Example System Interface Signals
1.7.6. Compiling the Design Example for Synthesis
1.7.7. Implementing the Design on the Development Kit
1.7.8. Running the Software Control Flow
1.7.9. Customizing the Design Example
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1.6.1.1. PLL
The design example requires four different clock domains—device clock, management clock, frame clock, and link clock.
Typically, the device clock is generated from an external converter or a clock device while the management clock (AVS clock) is generated from an on-board 100 MHz oscillator.
For instance, if the JESD204B IP core is configured at data rate of 6.144 Gbps, transceiver reference clock frequency of 153.6 MHz, and number of octets per frame (F) = 2, the example below indicates the PLL clock frequencies:
- device clock = transceiver reference clock frequency = 153.6 MHz
- link clock = 6144 / 40 = 153.6 MHz
- frame clock = 153.6 x 32 / (8 x 2) = 307.2 MHz
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