JESD204B Intel® FPGA IP Design Example User Guide: Intel® Quartus® Prime Standard Edition

ID 683094
Date 10/31/2022
Document Table of Contents Control Unit

The control unit has access to the CSR interface of the JESD204B IP core duplex base core, PLL reconfiguration, transceiver reconfiguration controller, and SPI master. The control unit also serves as a clock and reset unit (CRU) for the design example.

The control unit replaces the software-based Nios II processor to perform device configuration and initialization on the JESD204B duplex base core. This configuration and initialization process includes the transceivers, transport layer, pattern generator and checker, external converters (ADC/DAC), and clock devices over the SPI interface.

Figure 18. Control Unit Process Flow