JESD204B Intel® FPGA IP Design Example User Guide: Intel® Quartus® Prime Standard Edition

ID 683094
Date 10/31/2022
Document Table of Contents Software Functions Description

The software C code provided with the design example performs basic JESD204B link initialization and exits.

This section describes the functions used in the main.c code and also the macros library that facilitates access to the configuration and status registers (CSR) of the JESD204B design example system. These functions and macros provide the building blocks for you to customize the software code to your system specifications.