JESD204B Intel® FPGA IP Design Example User Guide: Intel® Quartus® Prime Standard Edition

ID 683094
Date 10/31/2022
Document Table of Contents

1.7.7. Implementing the Design on the Development Kit

The Target Development Kit option in the parameter editor window gives you the option to target the example design to a development kit. For the Nios II processor design example, you can target the design to the Arria 10 GX FPGA Development Kit.
Note: The hardware example design targets an Arria 10 ES3 device (10AX115S3F45E2SGE3). It cannot function correctly on an Arria 10 production device.
When you select this target, the Quartus Settings File (jesd204b_ed.qsf) is updated with the following changes:
  1. The target device is set to match the Arria 10 device on the Arria 10 GX FPGA development kit. The device part number is 10AX115S3F45E2SGE3.
  2. Pin assignments are added for selected signals listed in the Pin Assignments section.