JESD204B Intel® FPGA IP Design Example User Guide: Intel® Quartus® Prime Standard Edition

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ID 683094
Date 10/31/2022
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® FPGA IP Design Example User Guide
1. JESD204B Intel® FPGA IP Design Example User Guide x
1.1. JESD204B Design Example Quick Start Guide 1.2. Supported Configurations 1.3. Generic Design Example 1.4. Presets 1.5. Selecting and Generating the Design Example 1.6. Design Example with RTL State Machine Control Unit 1.7. Design Example with NIOS Control Unit 1.8. JESD204B Intel® FPGA IP Design Example User Guide Document Archives 1.9. Document Revision History for the JESD204B Intel® FPGA IP Design Example User Guide
1.1. JESD204B Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Compiling and Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Procedure 1.1.2.2. Design Example Parameters
1.1.3. Compiling and Simulating the Design x
1.1.3.1. Procedure
1.6. Design Example with RTL State Machine Control Unit x
1.6.1. Design Example Components 1.6.2. System Parameters 1.6.3. System Interface Signals 1.6.4. Example Feature: Dynamic Reconfiguration 1.6.5. Generating and Simulating the Design Example 1.6.6. Generating the Design Example For Compilation 1.6.7. Compiling the JESD204B IP Core Design Example
1.6.1. Design Example Components x
1.6.1.1. PLL 1.6.1.2. PLL Reconfiguration 1.6.1.3. Transceiver Reconfiguration Controller 1.6.1.4. Transceiver Reset Controller 1.6.1.5. Pattern Generator 1.6.1.6. Pattern Checker 1.6.1.7. Transport Layer 1.6.1.8. Serial Port Interface (SPI) 1.6.1.9. Control Unit
1.6.1.5. Pattern Generator x
1.6.1.5.1. Parallel PRBS Generator 1.6.1.5.2. Alternate Checkerboard Generator 1.6.1.5.3. Ramp Wave Generator
1.6.1.6. Pattern Checker x
1.6.1.6.1. Parallel PRBS Checker 1.6.1.6.2. Alternate Checkerboard Checker 1.6.1.6.3. Ramp Wave Checker
1.6.1.7. Transport Layer x
1.6.1.7.1. Supported System Configuration 1.6.1.7.2. Data Bit and Content Mapping Scheme 1.6.1.7.3. TX Path 1.6.1.7.4. RX Path
1.6.1.9. Control Unit x
1.6.1.9.1. Memory Block (ROM) 1.6.1.9.2. Finite State Machine (FSM)
1.6.2. System Parameters x
1.6.2.1. Run-Time Reconfiguration
1.6.4. Example Feature: Dynamic Reconfiguration x
1.6.4.1. Dynamic Reconfiguration Operation 1.6.4.2. MIF ROM
1.6.5. Generating and Simulating the Design Example x
1.6.5.1. Generating the Design Example Simulation Model 1.6.5.2. Simulating the JESD204B IP Core Design Example
1.7. Design Example with NIOS Control Unit x
1.7.1. Design Example Components 1.7.2. System Clocking 1.7.3. Nios II Processor Design Example Files 1.7.4. Nios II Processor Design Example System Parameters 1.7.5. Nios II Processor Design Example System Interface Signals 1.7.6. Compiling the Design Example for Synthesis 1.7.7. Implementing the Design on the Development Kit 1.7.8. Running the Software Control Flow 1.7.9. Customizing the Design Example
1.7.1. Design Example Components x
1.7.1.1. Platform Designer (Standard) System Component 1.7.1.2. Transport Layer 1.7.1.3. Test Pattern Generator 1.7.1.4. Test Pattern Checker
1.7.1.1. Platform Designer (Standard) System Component x
1.7.1.1.1. JESD204B Subsystem in Platform Designer (Standard) 1.7.1.1.2. Nios II Subsystem in Platform Designer (Standard) 1.7.1.1.3. Core PLL 1.7.1.1.4. PLL Reconfiguration Controller 1.7.1.1.5. SPI Master
1.7.7. Implementing the Design on the Development Kit x
1.7.7.1. Pin Assignments 1.7.7.2. Hardware Setup 1.7.7.3. Programming the Device
1.7.8. Running the Software Control Flow x
1.7.8.1. Executing the Software C Code 1.7.8.2. Software Parameters 1.7.8.3. Software Interrupt Service Routines (ISR) 1.7.8.4. Software Functions Description
1.7.8.4. Software Functions Description x
1.7.8.4.1. Functions in main.c Source File 1.7.8.4.2. Custom Peripheral Access Macros in macros.c Source File
1.7.9. Customizing the Design Example x
1.7.9.1. Modifying the JESD204B IP Core Parameters Post-Generation 1.7.9.2. Changing the Data Rate or Reference Clock Frequency 1.7.9.3. Implementing a Multi-Link Design
1.7.9.3. Implementing a Multi-Link Design x
1.7.9.3.1. Editing the Platform Designer (Standard) Project 1.7.9.3.2. Editing the Top Level HDL File 1.7.9.3.3. Editing the Software C Code
1. JESD204B Intel® FPGA IP Design Example User Guide

1.7.5. Nios II Processor Design Example System Interface Signals

Table 43.  System Interface Signals

Signal

Clock Domain

Direction

Description

Clocks and Resets
device_clk — Input

Reference clock for JESD204B data path.
mgmt_clk — Input

Reference clock for Nios II processor control path and all peripherals connected via Avalon-MM interconnect.

sma_clkout — Output

Clock output to SMA connector on board (for test only).
global_rst_n mgmt_clk Input

Global reset signal from the push button. This reset is an active low signal and the deassertion of this signal is synchronous to the rising-edge of mgmt_clk.

Signal

Clock Domain

Direction

Description

Serial Data
rx_serial_data[LINK*L-1:0] device_clk Input

Differential high speed serial input data. The clock is recovered from the serial data stream.

tx_serial_data[LINK*L-1:0] device_clk Output

Differential high speed serial output data. The clock is embedded in the serial data stream.

Signal

Clock Domain

Direction

Description

JESD204B
sysref_out mgmt_clk Output

SYSREF signal for JESD204B Subclass 1 implementation.

sync_n_out link_clk Output

Indicates a SYNC_N from the receiver. This is an active low signal and is asserted 0 to indicate a synchronization request or error reporting.

Signal

Clock Domain

Direction

Description

Avalon- ST User Data
avst_usr_din[LINK* TL_DATA_BUS_WIDTH-1:0] frame_clk Input TX data from the Avalon-ST source interface. The TL_DATA_BUS_WIDTH is determined by the following formulas:
  • If F = 1, TL_DATA_BUS_WIDTH = F1_FRAMECLK_DIV*8*1*L*N/N_PRIME
  • If F = 2, TL_DATA_BUS_WIDTH = F2_FRAMECLK_DIV*8*2*L*N/N_PRIME
  • If F = 4, TL_DATA_BUS_WIDTH = 8*4*L*N/N_PRIME
  • If F = 8, TL_DATA_BUS_WIDTH = 8*8*L*N/N_PRIME
avst_usr_din_valid[LINK-1:0] frame_clk Input

Indicates whether the data from the Avalon-ST source interface to the transport layer is valid or invalid.

  • 0—data is invalid
  • 1—data is valid
avst_usr_din_ready[LINK-1:0] frame_clk Output

Indicates that the transport layer is ready to accept data from the Avalon-ST source interface.

  • 0—transport layer is not ready to receive data
  • 1—transport layer is ready to receive data
avst_usr_dout[LINK* TL_DATA_BUS_WIDTH-1:0] frame_clk Output RX data to the Avalon-ST sink interface. The TL_DATA_BUS_WIDTH is determined by the following formulas:
  • If F = 1, TL_DATA_BUS_WIDTH = F1_FRAMECLK_DIV*8*1*L*N/N_PRIME
  • If F = 2, TL_DATA_BUS_WIDTH = F2_FRAMECLK_DIV*8*2*L*N/N_PRIME
  • If F = 4, TL_DATA_BUS_WIDTH = 8*4*L*N/N_PRIME
  • If F = 8, TL_DATA_BUS_WIDTH = 8*8*L*N/N_PRIME
avst_usr_dout_valid[LINK-1:0] frame_clk Output

Indicates whether the data from the transport layer to the Avalon-ST sink interface is valid or invalid.

  • 0—data is invalid
  • 1—data is valid
avst_usr_dout_ready[LINK-1:0] frame_clk Input

Indicates that the Avalon-ST sink interface is ready to accept data from the transport layer.

  • 0—Avalon-ST sink interface is not ready to receive data
  • 1—Avalon-ST sink interface is ready to receive data
avst_patchk_data_error [LINK-1:0] frame_clk Output

Output signal from pattern checker indicating a pattern check error.

Signal

Clock Domain

Direction

Description

SPI
spi_MISO spi_SCLK Input

Output data from a slave to the input of the master.

spi_MOSI spi_SCLK Output

Output data from the master to the inputs of the slaves.

spi_SCLK mgmt_clk Output

Clock driven by the master to slaves, to synchronize the data bits.

spi_SS_n[2:0] spi_SCLK Output

Active low select signal driven by the master to individual slaves, to select the target slave. Defaults to 3 bits.

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