JESD204B Intel® FPGA IP Design Example User Guide: Intel® Quartus® Prime Standard Edition

ID 683094
Date 10/31/2022
Document Table of Contents Run-Time Reconfiguration

The JESD204B IP core supports run-time reconfiguration for the LMF and data rate settings. The design example only demonstrates the following set of configuration.

To generate the design example with run-time reconfiguration enabled, the LMF and bonding mode parameters must match the default value listed in the table below.

Table 32.   Run-time Reconfiguration Demonstrated By The Design Example
Parameter Default Run-time Reconfiguration
LMF 222 112
Data Rate 6144 Mbps 3072 Mbps
Link Clock 153.6 MHz 76.8 MHz
Frame Clock 153.6 MHz 76.8 MHz
Bonding Mode Non-bonded Non-bonded