JESD204B Intel® FPGA IP Design Example User Guide: Intel® Quartus® Prime Standard Edition

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ID 683094
Date 10/31/2022
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® FPGA IP Design Example User Guide
1. JESD204B Intel® FPGA IP Design Example User Guide x
1.1. JESD204B Design Example Quick Start Guide 1.2. Supported Configurations 1.3. Generic Design Example 1.4. Presets 1.5. Selecting and Generating the Design Example 1.6. Design Example with RTL State Machine Control Unit 1.7. Design Example with NIOS Control Unit 1.8. JESD204B Intel® FPGA IP Design Example User Guide Document Archives 1.9. Document Revision History for the JESD204B Intel® FPGA IP Design Example User Guide
1.1. JESD204B Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Compiling and Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Procedure 1.1.2.2. Design Example Parameters
1.1.3. Compiling and Simulating the Design x
1.1.3.1. Procedure
1.6. Design Example with RTL State Machine Control Unit x
1.6.1. Design Example Components 1.6.2. System Parameters 1.6.3. System Interface Signals 1.6.4. Example Feature: Dynamic Reconfiguration 1.6.5. Generating and Simulating the Design Example 1.6.6. Generating the Design Example For Compilation 1.6.7. Compiling the JESD204B IP Core Design Example
1.6.1. Design Example Components x
1.6.1.1. PLL 1.6.1.2. PLL Reconfiguration 1.6.1.3. Transceiver Reconfiguration Controller 1.6.1.4. Transceiver Reset Controller 1.6.1.5. Pattern Generator 1.6.1.6. Pattern Checker 1.6.1.7. Transport Layer 1.6.1.8. Serial Port Interface (SPI) 1.6.1.9. Control Unit
1.6.1.5. Pattern Generator x
1.6.1.5.1. Parallel PRBS Generator 1.6.1.5.2. Alternate Checkerboard Generator 1.6.1.5.3. Ramp Wave Generator
1.6.1.6. Pattern Checker x
1.6.1.6.1. Parallel PRBS Checker 1.6.1.6.2. Alternate Checkerboard Checker 1.6.1.6.3. Ramp Wave Checker
1.6.1.7. Transport Layer x
1.6.1.7.1. Supported System Configuration 1.6.1.7.2. Data Bit and Content Mapping Scheme 1.6.1.7.3. TX Path 1.6.1.7.4. RX Path
1.6.1.9. Control Unit x
1.6.1.9.1. Memory Block (ROM) 1.6.1.9.2. Finite State Machine (FSM)
1.6.2. System Parameters x
1.6.2.1. Run-Time Reconfiguration
1.6.4. Example Feature: Dynamic Reconfiguration x
1.6.4.1. Dynamic Reconfiguration Operation 1.6.4.2. MIF ROM
1.6.5. Generating and Simulating the Design Example x
1.6.5.1. Generating the Design Example Simulation Model 1.6.5.2. Simulating the JESD204B IP Core Design Example
1.7. Design Example with NIOS Control Unit x
1.7.1. Design Example Components 1.7.2. System Clocking 1.7.3. Nios II Processor Design Example Files 1.7.4. Nios II Processor Design Example System Parameters 1.7.5. Nios II Processor Design Example System Interface Signals 1.7.6. Compiling the Design Example for Synthesis 1.7.7. Implementing the Design on the Development Kit 1.7.8. Running the Software Control Flow 1.7.9. Customizing the Design Example
1.7.1. Design Example Components x
1.7.1.1. Platform Designer (Standard) System Component 1.7.1.2. Transport Layer 1.7.1.3. Test Pattern Generator 1.7.1.4. Test Pattern Checker
1.7.1.1. Platform Designer (Standard) System Component x
1.7.1.1.1. JESD204B Subsystem in Platform Designer (Standard) 1.7.1.1.2. Nios II Subsystem in Platform Designer (Standard) 1.7.1.1.3. Core PLL 1.7.1.1.4. PLL Reconfiguration Controller 1.7.1.1.5. SPI Master
1.7.7. Implementing the Design on the Development Kit x
1.7.7.1. Pin Assignments 1.7.7.2. Hardware Setup 1.7.7.3. Programming the Device
1.7.8. Running the Software Control Flow x
1.7.8.1. Executing the Software C Code 1.7.8.2. Software Parameters 1.7.8.3. Software Interrupt Service Routines (ISR) 1.7.8.4. Software Functions Description
1.7.8.4. Software Functions Description x
1.7.8.4.1. Functions in main.c Source File 1.7.8.4.2. Custom Peripheral Access Macros in macros.c Source File
1.7.9. Customizing the Design Example x
1.7.9.1. Modifying the JESD204B IP Core Parameters Post-Generation 1.7.9.2. Changing the Data Rate or Reference Clock Frequency 1.7.9.3. Implementing a Multi-Link Design
1.7.9.3. Implementing a Multi-Link Design x
1.7.9.3.1. Editing the Platform Designer (Standard) Project 1.7.9.3.2. Editing the Top Level HDL File 1.7.9.3.3. Editing the Software C Code
1. JESD204B Intel® FPGA IP Design Example User Guide

1.7.8.1. Executing the Software C Code

To execute the software code and initialize the JESD204B link:

  1. Program the device on the board with the FPGA programming file as described in the Programming the Device section.
  2. In the Intel® Quartus® Prime software, navigate to the Tools menu and select Nios II Software Build Tools for Eclipse.
  3. In the Select a workspace dialog box, navigate to the software workspace, <your project> /ed_nios/software and click OK.
  4. Create a new Nios II application and board support package (BSP) from the template. On the File menu, navigate to New and click Nios II Application and BSP From Template.
  5. In the Nios II Application and BSP From Template window, enter the following information:
    • SOPC Information File Name: <your project> /ed_nios/jesd204b_ed_qsys.sopcinfo
    • Project name: jesd204_nios_ed 20
    • User default location: Checked
    • Templates: Blank Project
  6. Click Next. Verify that the default BSP name is jesd204_nios_ed_bsp, then click Finish. The Nios II application project (jesd204_nios_ed) and BSP (jesd204_nios_ed_bsp) appears in the Project Explorer window.
    Note: Whenever you modify and recompile the Quartus project, you must regenerate the BSP files. In the Project Explorer window, right-click the jesd204_nios_ed_bsp project, navigate to Nios II and click Generate. This regenerates the BSP files based on your most current compiled Quartus project settings.
  7. Import the design example source (*.c) and header (*.h) files into the application directory. In the Project Explorer window, right click on the jesd204_nios_ed project and click Import.
  8. In the Import window, select General > File System as the import source. Click Next>.
  9. Browse to the <your project> /ed_nios/software/source directory. Check the source box on the left panel. This selects all the source and header files in the source directory. Verify that the list of source and header files are as follows:
    • altera_jesd204_regs.h
    • functions.h
    • macros.h
    • main.h
    • macros.c
    • main.c
    Verify that the destination folder is jesd204_nios_ed. Click Finish. All the source and header files should be imported into the jesd204_nios_ed project directory.
  10. Right-click the jesd204_nios_ed_bsp project, navigate to Nios II and click BSP Editor. Under the Drivers tab, check the enable_small_driver box of the altera_avalon_jtag_uart_driver group and click Generate. This setting allows the compilation to proceed without connecting the interrupt ports of the JTAG UART module. After the BSP files have been generated, click Exit.
  11. Expand the jesd204_nios_ed application project in the Project Explorer window and verify that the folder contains all the source and header files.
  12. To compile the C code, navigate to the Project menu and select Build All. The compiler now compiles the C code into executable code.
  13. To download the executable code to the development board, navigate to the Run menu and select Run Configurations. In the Run Configurations window, double-click Nios II Hardware on the left panel. Check that all run configurations are correct, then click Run on the bottom right corner of the window.

The Intel® Quartus® Prime software downloads the executable code onto the board and the Nios II processor executes the code. The code performs the JESD204B link initialization sequence and exits. You can view the code execution results on the Nios II Console tab.

All printf statements in the C code print to this console window. Similarly, all user input functions like getc, gets, and scanf get user input from this console window. At the end of the initialization sequence, the code prints the JESD204B link status to the console. The following tables list the expected values of the link status register report.

Table 45.  TX Status 0 Register Bits
Bit Name Description Expected Binary Value
[0] SYNC_N value

0: Receiver is not in sync

1: Link is in sync

 1
[2:1] Data Link Layer (DLL) state

00: Code Group Synchronization (CGS)

01: Initial Lane Alignment Sequence (ILAS)

10: User Data Mode

11: D21.5 test mode

 10
Table 46.  RX Status 0 Register Bits
Bit Name Description Expected Binary Value
[0] SYNC_N value

0 – Receiver is not in sync

1 – Link is in sync

 1
Others — — Don’t care

The code also reports the status of the pattern checker. Any pattern checker errors that occur during the initialization period is flagged in the console window.

20 You can choose any name for the project. This project name is given for reference purposes only.
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