JESD204B Intel® FPGA IP Design Example User Guide: Intel® Quartus® Prime Standard Edition

ID 683094
Date 10/31/2022
Document Table of Contents Executing the Software C Code

To execute the software code and initialize the JESD204B link:

  1. Program the device on the board with the FPGA programming file as described in the Programming the Device section.
  2. In the Intel® Quartus® Prime software, navigate to the Tools menu and select Nios II Software Build Tools for Eclipse.
  3. In the Select a workspace dialog box, navigate to the software workspace, <your project> /ed_nios/software and click OK.
  4. Create a new Nios II application and board support package (BSP) from the template. On the File menu, navigate to New and click Nios II Application and BSP From Template.
  5. In the Nios II Application and BSP From Template window, enter the following information:
    • SOPC Information File Name: <your project> /ed_nios/jesd204b_ed_qsys.sopcinfo
    • Project name: jesd204_nios_ed 20
    • User default location: Checked
    • Templates: Blank Project
  6. Click Next. Verify that the default BSP name is jesd204_nios_ed_bsp, then click Finish. The Nios II application project (jesd204_nios_ed) and BSP (jesd204_nios_ed_bsp) appears in the Project Explorer window.
    Note: Whenever you modify and recompile the Quartus project, you must regenerate the BSP files. In the Project Explorer window, right-click the jesd204_nios_ed_bsp project, navigate to Nios II and click Generate. This regenerates the BSP files based on your most current compiled Quartus project settings.
  7. Import the design example source (*.c) and header (*.h) files into the application directory. In the Project Explorer window, right click on the jesd204_nios_ed project and click Import.
  8. In the Import window, select General > File System as the import source. Click Next>.
  9. Browse to the <your project> /ed_nios/software/source directory. Check the source box on the left panel. This selects all the source and header files in the source directory. Verify that the list of source and header files are as follows:
    • altera_jesd204_regs.h
    • functions.h
    • macros.h
    • main.h
    • macros.c
    • main.c
    Verify that the destination folder is jesd204_nios_ed. Click Finish. All the source and header files should be imported into the jesd204_nios_ed project directory.
  10. Right-click the jesd204_nios_ed_bsp project, navigate to Nios II and click BSP Editor. Under the Drivers tab, check the enable_small_driver box of the altera_avalon_jtag_uart_driver group and click Generate. This setting allows the compilation to proceed without connecting the interrupt ports of the JTAG UART module. After the BSP files have been generated, click Exit.
  11. Expand the jesd204_nios_ed application project in the Project Explorer window and verify that the folder contains all the source and header files.
  12. To compile the C code, navigate to the Project menu and select Build All. The compiler now compiles the C code into executable code.
  13. To download the executable code to the development board, navigate to the Run menu and select Run Configurations. In the Run Configurations window, double-click Nios II Hardware on the left panel. Check that all run configurations are correct, then click Run on the bottom right corner of the window.

The Intel® Quartus® Prime software downloads the executable code onto the board and the Nios II processor executes the code. The code performs the JESD204B link initialization sequence and exits. You can view the code execution results on the Nios II Console tab.

All printf statements in the C code print to this console window. Similarly, all user input functions like getc, gets, and scanf get user input from this console window. At the end of the initialization sequence, the code prints the JESD204B link status to the console. The following tables list the expected values of the link status register report.

Table 45.  TX Status 0 Register Bits
Bit Name Description Expected Binary Value
[0] SYNC_N value

0: Receiver is not in sync

1: Link is in sync

[2:1] Data Link Layer (DLL) state

00: Code Group Synchronization (CGS)

01: Initial Lane Alignment Sequence (ILAS)

10: User Data Mode

11: D21.5 test mode

Table 46.  RX Status 0 Register Bits
Bit Name Description Expected Binary Value
[0] SYNC_N value

0 – Receiver is not in sync

1 – Link is in sync

Others Don’t care

The code also reports the status of the pattern checker. Any pattern checker errors that occur during the initialization period is flagged in the console window.

20 You can choose any name for the project. This project name is given for reference purposes only.