JESD204B Intel® FPGA IP Design Example User Guide: Intel® Quartus® Prime Standard Edition

ID 683094
Date 10/31/2022
Document Table of Contents

1.7.2. System Clocking

The main reference clock for the design data path is the device_clk, which is supplied from an external source. The device_clk is the reference clock for the core PLL and the TX/RX transceiver reference clocks. The core PLL generates the link_clk and frame_clk from the device_clk. The link_clk clocks the JESD204B IP core link layer and link interface of the transport layer. The frame_clk clocks the transport layer, test pattern generator and checker modules, and any downstream modules. The external source supplies a clock called the mgmt_clk to clock the control path of the design (the Nios II subsystem and any modules connected to the Nios II via the Avalon-MM bus interconnect).

Table 39.  System Clocking for the Design Example
Note: The IOPLL input reference clock is sourcing from device clock through the global clock network. Sourcing reference clock from a cascaded PLL output, global clock or core clock network might introduce additional jitter to the IOPLL and transceiver PLL output. Refer to this KDB Answer for a workaround you should apply to the IP core in your design.
Clocks Description Source Modules Clocked
device_clk Reference clock for the data path Core PLL, ATX PLL, RX transceiver PLL
link_clk Link layer clock device_clk JESD204B IP core link layer, transport layer link interface
frame_clk Frame layer clock device_clk Transport layer, test pattern generator and checker, downstream modules
mgmt_clk Control plane clock Nios II subsystem and any modules connected to Nios II via Avalon-MM bus interconnect