JESD204B Intel® FPGA IP Design Example User Guide: Intel® Quartus® Prime Standard Edition

ID 683094
Date 10/31/2022
Document Table of Contents

1.3. Generic Design Example

If the JESD204B IP parameters that you select does not match any design example that is available, there is an option for you to generate a generic design example.
A generic design example is a design that has pre-selected IP parameters that matches the list of supported IP parameters for the design example.
Note: The generated generic example design may have IP parameters that differ from the parameters of your IP core. Modify the generic example design according to your system specifications.

The table below lists the parameters in the generic design example.

Table 7.   IP Parameter Settings for Generic Design Example
JESD204B IP Parameters Design Example
Generic RTL State Machine Control Generic Nios II Control
Devices Support V series and Arria 10 Arria 10
L 2 2
M 2 2
F 2 2
K 16 16
S 1 1
Wrapper Options Both Base and Phy Both Base and Phy
Data Path Duplex Duplex
JESD204B Subclass 1 1
Data Rate 6144 6144
PCS Option Enabled Hard PCS Enabled Hard PCS
Bonding Mode Bonded Non-bonded
Enable Transceiver Dynamic Reconfiguration No Yes
PLL/CDR Reference Clock Frequency 153.6 153.6
Enable Bit Reversal And Byte Reversal No No
N 16 16
N’ 16 16
CS 0 0
CF 0 0
High Density User Data Format (HD) 0 0
Enable scramble (SCR) Yes Yes
Enable Error Code Correction (ECC_EN) Yes Yes
6 Not applicable to Arria 10 devices.