JESD204B Intel® FPGA IP Design Example User Guide: Intel® Quartus® Prime Standard Edition

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ID 683094
Date 10/31/2022
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® FPGA IP Design Example User Guide
1. JESD204B Intel® FPGA IP Design Example User Guide x
1.1. JESD204B Design Example Quick Start Guide 1.2. Supported Configurations 1.3. Generic Design Example 1.4. Presets 1.5. Selecting and Generating the Design Example 1.6. Design Example with RTL State Machine Control Unit 1.7. Design Example with NIOS Control Unit 1.8. JESD204B Intel® FPGA IP Design Example User Guide Document Archives 1.9. Document Revision History for the JESD204B Intel® FPGA IP Design Example User Guide
1.1. JESD204B Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Compiling and Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Procedure 1.1.2.2. Design Example Parameters
1.1.3. Compiling and Simulating the Design x
1.1.3.1. Procedure
1.6. Design Example with RTL State Machine Control Unit x
1.6.1. Design Example Components 1.6.2. System Parameters 1.6.3. System Interface Signals 1.6.4. Example Feature: Dynamic Reconfiguration 1.6.5. Generating and Simulating the Design Example 1.6.6. Generating the Design Example For Compilation 1.6.7. Compiling the JESD204B IP Core Design Example
1.6.1. Design Example Components x
1.6.1.1. PLL 1.6.1.2. PLL Reconfiguration 1.6.1.3. Transceiver Reconfiguration Controller 1.6.1.4. Transceiver Reset Controller 1.6.1.5. Pattern Generator 1.6.1.6. Pattern Checker 1.6.1.7. Transport Layer 1.6.1.8. Serial Port Interface (SPI) 1.6.1.9. Control Unit
1.6.1.5. Pattern Generator x
1.6.1.5.1. Parallel PRBS Generator 1.6.1.5.2. Alternate Checkerboard Generator 1.6.1.5.3. Ramp Wave Generator
1.6.1.6. Pattern Checker x
1.6.1.6.1. Parallel PRBS Checker 1.6.1.6.2. Alternate Checkerboard Checker 1.6.1.6.3. Ramp Wave Checker
1.6.1.7. Transport Layer x
1.6.1.7.1. Supported System Configuration 1.6.1.7.2. Data Bit and Content Mapping Scheme 1.6.1.7.3. TX Path 1.6.1.7.4. RX Path
1.6.1.9. Control Unit x
1.6.1.9.1. Memory Block (ROM) 1.6.1.9.2. Finite State Machine (FSM)
1.6.2. System Parameters x
1.6.2.1. Run-Time Reconfiguration
1.6.4. Example Feature: Dynamic Reconfiguration x
1.6.4.1. Dynamic Reconfiguration Operation 1.6.4.2. MIF ROM
1.6.5. Generating and Simulating the Design Example x
1.6.5.1. Generating the Design Example Simulation Model 1.6.5.2. Simulating the JESD204B IP Core Design Example
1.7. Design Example with NIOS Control Unit x
1.7.1. Design Example Components 1.7.2. System Clocking 1.7.3. Nios II Processor Design Example Files 1.7.4. Nios II Processor Design Example System Parameters 1.7.5. Nios II Processor Design Example System Interface Signals 1.7.6. Compiling the Design Example for Synthesis 1.7.7. Implementing the Design on the Development Kit 1.7.8. Running the Software Control Flow 1.7.9. Customizing the Design Example
1.7.1. Design Example Components x
1.7.1.1. Platform Designer (Standard) System Component 1.7.1.2. Transport Layer 1.7.1.3. Test Pattern Generator 1.7.1.4. Test Pattern Checker
1.7.1.1. Platform Designer (Standard) System Component x
1.7.1.1.1. JESD204B Subsystem in Platform Designer (Standard) 1.7.1.1.2. Nios II Subsystem in Platform Designer (Standard) 1.7.1.1.3. Core PLL 1.7.1.1.4. PLL Reconfiguration Controller 1.7.1.1.5. SPI Master
1.7.7. Implementing the Design on the Development Kit x
1.7.7.1. Pin Assignments 1.7.7.2. Hardware Setup 1.7.7.3. Programming the Device
1.7.8. Running the Software Control Flow x
1.7.8.1. Executing the Software C Code 1.7.8.2. Software Parameters 1.7.8.3. Software Interrupt Service Routines (ISR) 1.7.8.4. Software Functions Description
1.7.8.4. Software Functions Description x
1.7.8.4.1. Functions in main.c Source File 1.7.8.4.2. Custom Peripheral Access Macros in macros.c Source File
1.7.9. Customizing the Design Example x
1.7.9.1. Modifying the JESD204B IP Core Parameters Post-Generation 1.7.9.2. Changing the Data Rate or Reference Clock Frequency 1.7.9.3. Implementing a Multi-Link Design
1.7.9.3. Implementing a Multi-Link Design x
1.7.9.3.1. Editing the Platform Designer (Standard) Project 1.7.9.3.2. Editing the Top Level HDL File 1.7.9.3.3. Editing the Software C Code
1. JESD204B Intel® FPGA IP Design Example User Guide

1.7.7.1. Pin Assignments

The serial data (tx_serial_data [n] and rx_serial_data[n]) pin assignments are shown for the maximum number of transceiver lanes supported by the design example, which is L = 8. For other configurations where L < 8, a subset of the serial data pin assignments are selected.

Table 44.  Top Level Interface Ports and its Corresponding Pin AssignmentsThe interface ports of the top level HDL file (jesd204b_ed.sv) with its corresponding FPGA pin assignments on the Arria 10 FPGA development board are listed in the table below.
Interface Port Name FPGA Pin Number I/O Standard Direction Board Source/Destination
global_rst_n T12 1.8 V Input User PB0 push-button
device_clk AN8 LVDS Input On-board Si5338 programmable oscillator (Output: CLK1B)
device_clk (n) AN7 LVDS Input

On-board Si5338 programmable oscillator

(Output: CLK1A)

mgmt_clk AR36 LVDS Input On-board Si570 programmable oscillator (Output: 100 Mhz)
mgmt_clk(n) AR37 LVDS Input On-board Si570 programmable oscillator (Output: 100 Mhz)
sma_clkout E24 1.8 V Output SMA clock out
spi_MISO AR22 1.8 V Input FMC Port A connector
spi_MOSI AR11 1.8 V Output FMC Port A connector
spi_SCLK AT10 1.8 V Output FMC Port A connector
spi_SS_n[0] AV14 1.8 V Output FMC Port A connector
tx_serial_data[7] AW3 High Speed Differential I/O Output FMC Port A connector
tx_serial_data[7] (n) AW4 High Speed Differential I/O Output FMC Port A connector
tx_serial_data[6] AY1 High Speed Differential I/O Output FMC Port A connector
tx_serial_data[6] (n) AY2 High Speed Differential I/O Output FMC Port A connector
tx_serial_data[5] BA3 High Speed Differential I/O Output FMC Port A connector
tx_serial_data[5] (n) BA4 High Speed Differential I/O Output FMC Port A connector
tx_serial_data[4] BB1 High Speed Differential I/O Output FMC Port A connector
tx_serial_data[4] (n) BB2 High Speed Differential I/O Output FMC Port A connector
tx_serial_data[3] BC3 High Speed Differential I/O Output FMC Port A connector
tx_serial_data[3] (n) BC4 High Speed Differential I/O Output FMC Port A connector
tx_serial_data[2] BB5 High Speed Differential I/O Output FMC Port A connector
tx_serial_data[2] (n) BB6 High Speed Differential I/O Output FMC Port A connector
tx_serial_data[1] BD5 High Speed Differential I/O Output FMC Port A connector
tx_serial_data[1] (n) BD6 High Speed Differential I/O Output FMC Port A connector
tx_serial_data[0] BC7 High Speed Differential I/O Output FMC Port A connector
tx_serial_data[0] (n) BC8 High Speed Differential I/O Output FMC Port A connector
rx_serial_data[7] AM5 High Speed Differential I/O Input FMC Port A connector
rx_serial_data[7] (n) AM6 High Speed Differential I/O Input FMC Port A connector
rx_serial_data[6] AN3 High Speed Differential I/O Input FMC Port A connector
rx_serial_data[6] (n) AN4 High Speed Differential I/O Input FMC Port A connector
rx_serial_data[5] AP5 High Speed Differential I/O Input FMC Port A connector
rx_serial_data[5] (n) AP6 High Speed Differential I/O Input FMC Port A connector
rx_serial_data[4] AT5 High Speed Differential I/O Input FMC Port A connector
rx_serial_data[4] (n) AT6 High Speed Differential I/O Input FMC Port A connector
rx_serial_data[3] AV5 High Speed Differential I/O Input FMC Port A connector
rx_serial_data[3] (n) AV6 High Speed Differential I/O Input FMC Port A connector
rx_serial_data[2] AY5 High Speed Differential I/O Input FMC Port A connector
rx_serial_data[2] (n) AY6 High Speed Differential I/O Input FMC Port A connector
rx_serial_data[1] BA7 High Speed Differential I/O Input FMC Port A connector
rx_serial_data[1] (n) BA8 High Speed Differential I/O Input FMC Port A connector
rx_serial_data[0] AW7 High Speed Differential I/O Input FMC Port A connector
rx_serial_data[0] (n) AW8 High Speed Differential I/O Input FMC Port A connector
sysref_out AV11 LVDS Output FMC Port A connector
sysref_out (n) AW11 LVDS Output FMC Port A connector
sync_n_out AN20 LVDS Output FMC Port A connector
sync_n_out (n) AP19 LVDS Output FMC Port A connector
Level Two Title