JESD204B Intel® FPGA IP Design Example User Guide: Intel® Quartus® Prime Standard Edition

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ID 683094
Date 10/31/2022
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® FPGA IP Design Example User Guide
1. JESD204B Intel® FPGA IP Design Example User Guide x
1.1. JESD204B Design Example Quick Start Guide 1.2. Supported Configurations 1.3. Generic Design Example 1.4. Presets 1.5. Selecting and Generating the Design Example 1.6. Design Example with RTL State Machine Control Unit 1.7. Design Example with NIOS Control Unit 1.8. JESD204B Intel® FPGA IP Design Example User Guide Document Archives 1.9. Document Revision History for the JESD204B Intel® FPGA IP Design Example User Guide
1.1. JESD204B Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Compiling and Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Procedure 1.1.2.2. Design Example Parameters
1.1.3. Compiling and Simulating the Design x
1.1.3.1. Procedure
1.6. Design Example with RTL State Machine Control Unit x
1.6.1. Design Example Components 1.6.2. System Parameters 1.6.3. System Interface Signals 1.6.4. Example Feature: Dynamic Reconfiguration 1.6.5. Generating and Simulating the Design Example 1.6.6. Generating the Design Example For Compilation 1.6.7. Compiling the JESD204B IP Core Design Example
1.6.1. Design Example Components x
1.6.1.1. PLL 1.6.1.2. PLL Reconfiguration 1.6.1.3. Transceiver Reconfiguration Controller 1.6.1.4. Transceiver Reset Controller 1.6.1.5. Pattern Generator 1.6.1.6. Pattern Checker 1.6.1.7. Transport Layer 1.6.1.8. Serial Port Interface (SPI) 1.6.1.9. Control Unit
1.6.1.5. Pattern Generator x
1.6.1.5.1. Parallel PRBS Generator 1.6.1.5.2. Alternate Checkerboard Generator 1.6.1.5.3. Ramp Wave Generator
1.6.1.6. Pattern Checker x
1.6.1.6.1. Parallel PRBS Checker 1.6.1.6.2. Alternate Checkerboard Checker 1.6.1.6.3. Ramp Wave Checker
1.6.1.7. Transport Layer x
1.6.1.7.1. Supported System Configuration 1.6.1.7.2. Data Bit and Content Mapping Scheme 1.6.1.7.3. TX Path 1.6.1.7.4. RX Path
1.6.1.9. Control Unit x
1.6.1.9.1. Memory Block (ROM) 1.6.1.9.2. Finite State Machine (FSM)
1.6.2. System Parameters x
1.6.2.1. Run-Time Reconfiguration
1.6.4. Example Feature: Dynamic Reconfiguration x
1.6.4.1. Dynamic Reconfiguration Operation 1.6.4.2. MIF ROM
1.6.5. Generating and Simulating the Design Example x
1.6.5.1. Generating the Design Example Simulation Model 1.6.5.2. Simulating the JESD204B IP Core Design Example
1.7. Design Example with NIOS Control Unit x
1.7.1. Design Example Components 1.7.2. System Clocking 1.7.3. Nios II Processor Design Example Files 1.7.4. Nios II Processor Design Example System Parameters 1.7.5. Nios II Processor Design Example System Interface Signals 1.7.6. Compiling the Design Example for Synthesis 1.7.7. Implementing the Design on the Development Kit 1.7.8. Running the Software Control Flow 1.7.9. Customizing the Design Example
1.7.1. Design Example Components x
1.7.1.1. Platform Designer (Standard) System Component 1.7.1.2. Transport Layer 1.7.1.3. Test Pattern Generator 1.7.1.4. Test Pattern Checker
1.7.1.1. Platform Designer (Standard) System Component x
1.7.1.1.1. JESD204B Subsystem in Platform Designer (Standard) 1.7.1.1.2. Nios II Subsystem in Platform Designer (Standard) 1.7.1.1.3. Core PLL 1.7.1.1.4. PLL Reconfiguration Controller 1.7.1.1.5. SPI Master
1.7.7. Implementing the Design on the Development Kit x
1.7.7.1. Pin Assignments 1.7.7.2. Hardware Setup 1.7.7.3. Programming the Device
1.7.8. Running the Software Control Flow x
1.7.8.1. Executing the Software C Code 1.7.8.2. Software Parameters 1.7.8.3. Software Interrupt Service Routines (ISR) 1.7.8.4. Software Functions Description
1.7.8.4. Software Functions Description x
1.7.8.4.1. Functions in main.c Source File 1.7.8.4.2. Custom Peripheral Access Macros in macros.c Source File
1.7.9. Customizing the Design Example x
1.7.9.1. Modifying the JESD204B IP Core Parameters Post-Generation 1.7.9.2. Changing the Data Rate or Reference Clock Frequency 1.7.9.3. Implementing a Multi-Link Design
1.7.9.3. Implementing a Multi-Link Design x
1.7.9.3.1. Editing the Platform Designer (Standard) Project 1.7.9.3.2. Editing the Top Level HDL File 1.7.9.3.3. Editing the Software C Code
1. JESD204B Intel® FPGA IP Design Example User Guide

1.7.3. Nios II Processor Design Example Files

The design example is stored in the <your project> /ed_nios file directory. For the design example with Nios II processor control unit, only the synthesis flow is available; simulation flow is not available.

Table 40.  Design Example FilesThis table lists the important folders and files in the ed_nios file directory.

File Type

File/Folder

Description

Quartus project files

jesd204b_ed.qpf

Quartus project file.

jesd204b_ed.qsf

Quartus settings file.
output_files Folder containing output files from Quartus compilation (for example, reports or sof)
Verilog HDL design files

jesd204b_ed.sv

Top level HDL.

jesd204b_ed.sdc

Synopsys Design Constraints (SDC) file containing all timing/placement constraints.
transport_layer Folder containing assembler and de-assembler HDL.
pattern Folder containing the test pattern generator and checker HDL.
spi_mosi_oe.v Output buffer RTL.
switch_debouncer.v Switch debouncer RTL.
Platform Designer (Standard) Projects

jesd204b_ed_qsys.qsys

Top level Platform Designer (Standard) system project.

jesd204b_subsystem.qsys

JESD204B subsystem (refer to related information)
se_outbuf_1bit.qsys Output buffer module.
se_outbuf_1bit Folder containing the output buffer module.

nios_subsystem.qsys

Nios II subsystem (refer to related information)
jesd204b_ed_qsys Folder containing generated HDL files from jesd204b_ed_qsys.qsys.
*.sopcinfo Files containing system information for software project building (refer to related information) .
Software files software

Folder containing all software-related files (detailed description in the Software File Directory table).

There are two folders for the software files:

  • jesd204_nios_ed—contains all user source and header files.
  • jesd204_nios_ed_bsp—board support package (BSP) that contains system files.
Table 41.  Software File Directory

File Type

File

Description

Header files (in jesd204_nios_ed folder)

altera_jesd204_qsys_regs.h

Offsets, masks, and bit position definitions for peripherals in Platform Designer (Standard) system that do not have standard access libraries. This includes the following peripherals:

  • JESD204B TX and RX CSR
  • Reset sequencer
  • PIO control
  • PIO status
  • Core PLL reconfiguration

main.h

General user parameter definitions.

functions.h

Contains function prototype definitions of sub-functions in main.c.

macros.h

Contains function prototype definitions of macro functions in macros.c.
Source files (in jesd204_nios_ed folder)

main.c

Main C program. Also contain sub functions.

macros.c

JESD204B Platform Designer (Standard) system device access macros.

System files (in jesd204_nios_ed_bsp folder)

system.h

BSP-generated header file containing Platform Designer (Standard) system-specific parameters such as:
  • Peripheral base addresses
  • Interrupt controller IDs
  • IRQ priorities
Attention: Do not edit this auto-generated header file.
Related Information
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