JESD204B Intel® FPGA IP Design Example User Guide: Intel® Quartus® Prime Standard Edition

ID 683094
Date 10/31/2022

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Document Table of Contents Editing the Platform Designer (Standard) Project

  1. Open the top level system, jesd204b_ed_qsys.qsys, in Platform Designer (Standard).
  2. Each JESD204B link is represented by a single jesd204b_subsystem instantiation. To implement multi-links in Platform Designer (Standard), duplicate the jesd204b_subsystem instantiations. Right-click the jesd204b_subsystem_0 module and select Duplicate. This duplicates the jesd204b_subsystem_0 module to a new module called jesd204b_subsystem_1.
  3. Connect the jesd204b_subsystem_1 ports as shown in the table below. Any ports not described in the table below should be exported. To export a port, click the Double-click to export label in the Export column of the System Contents tab.
    Ports for jesd204b_subsystem_1 Module Connection
    device_clk device_clk.clk
    do_not_connect_reset_0 mgmt_clk.clk_reset
    do_not_connect_reset_1 mgmt_clk.clk_reset
    do_not_connect_reset_2 mgmt_clk.clk_reset
    frame_clk frame_clk.clk
    jesd204b_jesd204_rx_int nios_subsystem.nios2_d_irq
    jesd204b_jesd204_tx_int nios_subsystem.nios2_d_irq
    link_clk link_clk.clk
    mgmt_clk mgmt_clk.clk
    mgmt_reset reset_controller_0.reset_out
    mm_bridge_s0 nios_subsystem.jesd204b_subsystem_mm_bridge_0_m0
    reset_seq_irq nios_subsystem.nios2_d_irq
    reset_seq_pll_reset (Do not connect)
    reset_seq_reset_in0 reset_controller_0.reset_out
  4. Adjust the interrupt priorities of the interrupt ports (jesd204b_jesd204_rx_int, jesd204b_jesd204_tx_int, and reset_seq_irq) in the new jesd204b_subsystem_1 module to meet your system specifications. Click and edit the priority number of the relevant ports in the IRQ column of the System Contents tab. The lower the priority number, the higher the priority.
  5. Assign the address map of the jesd204b_subsystem_1 module in the Address Map tab. Bits 16-19 of the nios_subsystem-to-jesd204b_subsystem Avalon-MM bridge are reserved to support multi-links. Assign the address map according to the figure shown below. Bits 16-19 in the address map denotes the link indicator. For subsequent links, increment the link indicator accordingly. The system can support up to 16 links.
    Figure 31. Multi-Link Address Map
  6. Repeat steps 2 – 5 for subsequent links in your design.
  7. Click Generate HDL to generate the design files needed for Quartus compilation.
  8. After the HDL generation is completed, click Finish to save your Platform Designer (Standard) settings and exit the Platform Designer (Standard) window.