JESD204B Intel® FPGA IP Design Example User Guide: Intel® Quartus® Prime Standard Edition

ID 683094
Date 10/31/2022

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1.6.7. Compiling the JESD204B IP Core Design Example

You can use the generated .qip file to include relevant files into your project. Generate the Intel® Quartus® Prime synthesis compilation files by running the script (gen_quartus_synth.tcl) located in the <example_design_directory>/ed_synth/ directory.

Note: If you use the Tcl console in the Intel® Quartus® Prime software to generate the gen_quartus_synth.tcl script, close all Intel® Quartus® Prime project before you start generating.

To compile your design using the Intel® Quartus® Prime software , follow these steps:

  1. Launch the Intel® Quartus® Prime software.
  2. On the File menu, click Open Project > Select <example_design_directory>/ed_synth/example_design/.
  3. Select jesd204b_ed.qpf. 17
  4. On the Processing menu, click Start Compilation.

    At the end of the compilation, the Intel® Quartus® Prime software provides a pass/fail indication.

17 This is the default quartus project file that the Intel® Quartus® Prime software automatically generates. You can edit this file and the .qsf file according to your design preference.