JESD204B Intel® FPGA IP Design Example User Guide: Intel® Quartus® Prime Standard Edition

Download PDF
ID 683094
Date 10/31/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® FPGA IP Design Example User Guide
1. JESD204B Intel® FPGA IP Design Example User Guide x
1.1. JESD204B Design Example Quick Start Guide 1.2. Supported Configurations 1.3. Generic Design Example 1.4. Presets 1.5. Selecting and Generating the Design Example 1.6. Design Example with RTL State Machine Control Unit 1.7. Design Example with NIOS Control Unit 1.8. JESD204B Intel® FPGA IP Design Example User Guide Document Archives 1.9. Document Revision History for the JESD204B Intel® FPGA IP Design Example User Guide
1.1. JESD204B Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Compiling and Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Procedure 1.1.2.2. Design Example Parameters
1.1.3. Compiling and Simulating the Design x
1.1.3.1. Procedure
1.6. Design Example with RTL State Machine Control Unit x
1.6.1. Design Example Components 1.6.2. System Parameters 1.6.3. System Interface Signals 1.6.4. Example Feature: Dynamic Reconfiguration 1.6.5. Generating and Simulating the Design Example 1.6.6. Generating the Design Example For Compilation 1.6.7. Compiling the JESD204B IP Core Design Example
1.6.1. Design Example Components x
1.6.1.1. PLL 1.6.1.2. PLL Reconfiguration 1.6.1.3. Transceiver Reconfiguration Controller 1.6.1.4. Transceiver Reset Controller 1.6.1.5. Pattern Generator 1.6.1.6. Pattern Checker 1.6.1.7. Transport Layer 1.6.1.8. Serial Port Interface (SPI) 1.6.1.9. Control Unit
1.6.1.5. Pattern Generator x
1.6.1.5.1. Parallel PRBS Generator 1.6.1.5.2. Alternate Checkerboard Generator 1.6.1.5.3. Ramp Wave Generator
1.6.1.6. Pattern Checker x
1.6.1.6.1. Parallel PRBS Checker 1.6.1.6.2. Alternate Checkerboard Checker 1.6.1.6.3. Ramp Wave Checker
1.6.1.7. Transport Layer x
1.6.1.7.1. Supported System Configuration 1.6.1.7.2. Data Bit and Content Mapping Scheme 1.6.1.7.3. TX Path 1.6.1.7.4. RX Path
1.6.1.9. Control Unit x
1.6.1.9.1. Memory Block (ROM) 1.6.1.9.2. Finite State Machine (FSM)
1.6.2. System Parameters x
1.6.2.1. Run-Time Reconfiguration
1.6.4. Example Feature: Dynamic Reconfiguration x
1.6.4.1. Dynamic Reconfiguration Operation 1.6.4.2. MIF ROM
1.6.5. Generating and Simulating the Design Example x
1.6.5.1. Generating the Design Example Simulation Model 1.6.5.2. Simulating the JESD204B IP Core Design Example
1.7. Design Example with NIOS Control Unit x
1.7.1. Design Example Components 1.7.2. System Clocking 1.7.3. Nios II Processor Design Example Files 1.7.4. Nios II Processor Design Example System Parameters 1.7.5. Nios II Processor Design Example System Interface Signals 1.7.6. Compiling the Design Example for Synthesis 1.7.7. Implementing the Design on the Development Kit 1.7.8. Running the Software Control Flow 1.7.9. Customizing the Design Example
1.7.1. Design Example Components x
1.7.1.1. Platform Designer (Standard) System Component 1.7.1.2. Transport Layer 1.7.1.3. Test Pattern Generator 1.7.1.4. Test Pattern Checker
1.7.1.1. Platform Designer (Standard) System Component x
1.7.1.1.1. JESD204B Subsystem in Platform Designer (Standard) 1.7.1.1.2. Nios II Subsystem in Platform Designer (Standard) 1.7.1.1.3. Core PLL 1.7.1.1.4. PLL Reconfiguration Controller 1.7.1.1.5. SPI Master
1.7.7. Implementing the Design on the Development Kit x
1.7.7.1. Pin Assignments 1.7.7.2. Hardware Setup 1.7.7.3. Programming the Device
1.7.8. Running the Software Control Flow x
1.7.8.1. Executing the Software C Code 1.7.8.2. Software Parameters 1.7.8.3. Software Interrupt Service Routines (ISR) 1.7.8.4. Software Functions Description
1.7.8.4. Software Functions Description x
1.7.8.4.1. Functions in main.c Source File 1.7.8.4.2. Custom Peripheral Access Macros in macros.c Source File
1.7.9. Customizing the Design Example x
1.7.9.1. Modifying the JESD204B IP Core Parameters Post-Generation 1.7.9.2. Changing the Data Rate or Reference Clock Frequency 1.7.9.3. Implementing a Multi-Link Design
1.7.9.3. Implementing a Multi-Link Design x
1.7.9.3.1. Editing the Platform Designer (Standard) Project 1.7.9.3.2. Editing the Top Level HDL File 1.7.9.3.3. Editing the Software C Code
1. JESD204B Intel® FPGA IP Design Example User Guide

1.7.9.1. Modifying the JESD204B IP Core Parameters Post-Generation

In the event that the design examples available does not suit your desired JESD204B IP parameter configuration, you can generate a generic example design and then manually modify the parameters to meet your specifications.
  1. Generate a generic design example with Nios II control unit.
  2. Open the top level Platform Designer (Standard) system (jesd204b_ed_qsys.qsys) in Platform Designer (Standard).
  3. In the Platform Designer (Standard) window, navigate to the File menu and click Open. Select jesd204b_subsystem.qsys and click Open.
  4. In the System Contents tab, double-click the jesd204b module. This brings up the parameter editor that shows the current parameter settings of the JESD204B IP core. This is the duplicate JESD204B IP core that is generated in the design example folder, not the JESD204B IP core that is generated from the IP tab of the parameter editor, which is stored in a different folder.
  5. Modify the IP core parameters of the jesd204b module as per your system specifications. When you are done, navigate to the File menu and click Save.
  6. In the File menu, click Open. Select the top level Platform Designer (Standard) project, jesd204b_ed_qsys.qsys and click Open.
  7. Verify that the jesd204b_subsystem.qsys project has been updated with the new IP parameters for the jesd204b module. Right-click the jesd204b_subsystem_0 module and select Drill into subsystem. The jesd204b_subsystem.qsys project opens in the Platform Designer (Standard) window. In the System Contents tab, double-click on the jesd204b module and verify that the parameters in the parameters tab match the ones that you have updated earlier. When you are done verifying, click Move to the top of hierarchy to move back to the jesd204b_ed_qsys.qsys view.
  8. Click Generate HDL to generate the HDL files needed for Quartus compilation.
  9. After the HDL generation is completed, click Finish to save your Platform Designer (Standard) settings and exit the Platform Designer (Standard) window.
  10. You have to manually change the system parameters in the top level RTL file to match the parameters that you set in the Platform Designer (Standard) project, if applicable. Open the top level RTL file (jesd204b_ed.sv) in any text editor of your choice.
  11. Modify the system parameters at the top of the file to match the new JESD204B IP core settings in the Platform Designer (Standard) project, if applicable. Refer to the Nios II Processor Design Example System Parameters for more details on the system parameters.
  12. Save the file and compile the design in Intel® Quartus® Prime software as per the instructions in the Compiling the Design Example for Synthesis.
Level Two Title