JESD204B Intel® FPGA IP Design Example User Guide: Intel® Quartus® Prime Standard Edition

ID 683094
Date 10/31/2022

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Document Table of Contents

1.7.1. Design Example Components

The Nios II processor control unit design example for the JESD204B IP core consists of the following components:
  • Platform Designer (Standard) system
    • JESD204B subsystem
    • Nios II subsystem
    • Core PLL
    • PLL reconfiguration controller
    • Serial Port Interface (SPI) – master module
  • Test pattern generator
  • Test pattern checker
  • Assembler and deassembler (in the transport layer)

The following sections describe in detail the function of each component.