JESD204B Intel® FPGA IP Design Example User Guide: Intel® Quartus® Prime Standard Edition

ID 683094
Date 10/31/2022
Document Table of Contents

1.7.6. Compiling the Design Example for Synthesis

After generating the design example, all the necessary files for synthesis are stored in the <your project> /ed_nios directory.
To compile the design using the Intel® Quartus® Prime software, follow these steps:
  1. Launch the Intel® Quartus® Prime software.
  2. On the File menu, click Open Project.
  3. Navigate to your project directory and select the Quartus project file (jesd204b_ed.qpf). Click Open.
    The Quartus project is now open in the Project Navigator window. If required, you can modify the HDL files and Platform Designer (Standard) projects to customize the design configurations to your specifications.
  4. On the Processing menu, select Start Compilation to compile the HDL.
    The Intel® Quartus® Prime software compiles the design and indicates the compilation status in the Tasks window.

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