JESD204B Intel® FPGA IP Design Example User Guide: Intel® Quartus® Prime Standard Edition

ID 683094
Date 10/31/2022
Document Table of Contents Procedure

This is a general procedure on how to generate the JESD204B design example.

To generate the design example from the IP parameter editor:

  1. In the IP Catalog (Tools > IP Catalog), locate and select JESD204B. The IP parameter editor appears.
  2. Specify a top-level name and the folder for your custom IP variation, and the target device. Click OK.
  3. Select a design from the Presets library. When you select a design, the system automatically populates the IP parameters for the design.
    Note: If you select another design, the settings of the IP parameters change accordingly.
  4. Specify the parameters for your design.
  5. Click the Generate Example Design button.
The software generates all design files in the sub-directories. These files are required to run simulation, compilation, and hardware testing.