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1.1. JESD204B Design Example Quick Start Guide
1.2. Supported Configurations
1.3. Generic Design Example
1.4. Presets
1.5. Selecting and Generating the Design Example
1.6. Design Example with RTL State Machine Control Unit
1.7. Design Example with NIOS Control Unit
1.8. JESD204B Intel® FPGA IP Design Example User Guide Document Archives
1.9. Document Revision History for the JESD204B Intel® FPGA IP Design Example User Guide
1.7.1. Design Example Components
1.7.2. System Clocking
1.7.3. Nios II Processor Design Example Files
1.7.4. Nios II Processor Design Example System Parameters
1.7.5. Nios II Processor Design Example System Interface Signals
1.7.6. Compiling the Design Example for Synthesis
1.7.7. Implementing the Design on the Development Kit
1.7.8. Running the Software Control Flow
1.7.9. Customizing the Design Example
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1.1.2.1. Procedure
This is a general procedure on how to generate the JESD204B design example.
To generate the design example from the IP parameter editor:
- In the IP Catalog (Tools > IP Catalog), locate and select JESD204B. The IP parameter editor appears.
- Specify a top-level name and the folder for your custom IP variation, and the target device. Click OK.
- Select a design from the Presets library. When you select a design, the system automatically populates the IP parameters for the design.
Note: If you select another design, the settings of the IP parameters change accordingly.
- Specify the parameters for your design.
- Click the Generate Example Design button.
The software generates all design files in the sub-directories. These files are required to run simulation, compilation, and hardware testing.
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