JESD204B Intel® FPGA IP Design Example User Guide: Intel® Quartus® Prime Standard Edition
ID
683094
Date
10/31/2022
Public
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1.1. JESD204B Design Example Quick Start Guide
1.2. Supported Configurations
1.3. Generic Design Example
1.4. Presets
1.5. Selecting and Generating the Design Example
1.6. Design Example with RTL State Machine Control Unit
1.7. Design Example with NIOS Control Unit
1.8. JESD204B Intel® FPGA IP Design Example User Guide Document Archives
1.9. Document Revision History for the JESD204B Intel® FPGA IP Design Example User Guide
1.7.1. Design Example Components
1.7.2. System Clocking
1.7.3. Nios II Processor Design Example Files
1.7.4. Nios II Processor Design Example System Parameters
1.7.5. Nios II Processor Design Example System Interface Signals
1.7.6. Compiling the Design Example for Synthesis
1.7.7. Implementing the Design on the Development Kit
1.7.8. Running the Software Control Flow
1.7.9. Customizing the Design Example
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1.7.9. Customizing the Design Example
Use the following guidelines if you want to customize the design example that you generate from the IP core's parameter editor.