JESD204B Intel® FPGA IP Design Example User Guide: Intel® Quartus® Prime Standard Edition

ID 683094
Date 10/31/2022
Public
Document Table of Contents

1.7.1.2. Transport Layer

The transport layer in the JESD204B IP core consists of an assembler at the TX path and a deassembler at the RX path. The transport layer for both the TX and RX path is implemented in the top level RTL file, not in the Platform Designer (Standard) project.

The transport layer provides the following services to the application layer (AL) and the DLL:

  • The assembler at the TX path:
    • maps the conversion samples from the AL (through the Avalon® streaming interface) to a specific format of non-scrambled octets, before streaming them to the DLL.
    • reports AL error to the DLL if it encounters a specific error condition on the Avalon® streaming interface during TX data streaming.
  • The deassembler at the RX path:
    • maps the descrambled octets from the DLL to a specific conversion sample format before streaming them to the AL (through the Avalon® streaming interface).
    • reports AL error to the DLL if it encounters a specific error condition on the Avalon® streaming interface during RX data streaming.

The transport layer has many customization options and you may modify the transport layer RTL to customize it to your specifications. Furthermore, for certain parameters like L, F, and N, the transport layer shares the CSR values with the JESD204B IP core. This means that any dynamic reconfiguration operation that affects those values for the JESD204B IP core affects the transport layer in the same way. By default, the software does not contain any dynamic reconfiguration features but you can use the Platform Designer (Standard) system to implement such feature in the software.

For more details on the implementation of the transport layer in RTL and customization options, refer to chapter 5.