JESD204B Intel® FPGA IP Design Example User Guide: Intel® Quartus® Prime Standard Edition

ID 683094
Date 10/31/2022
Document Table of Contents Finite State Machine (FSM)

The steps below describe the FSM flow:
  1. Initialize the SPI:
    1. Perform a read transaction from the ROM on per word basis and write to the SPI master for SPI write transaction to the external SPI slave.
    2. Perform a read transaction from the next ROM and perform the same SPI write transaction to next SPI slave.
  2. Initialize the JESD204B IP base core, transport layer, pattern generator, and pattern checker upon successful initialization of the transceiver.