JESD204B Intel® FPGA IP Design Example User Guide: Intel® Quartus® Prime Standard Edition

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Date 10/31/2022
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® FPGA IP Design Example User Guide
1. JESD204B Intel® FPGA IP Design Example User Guide x
1.1. JESD204B Design Example Quick Start Guide 1.2. Supported Configurations 1.3. Generic Design Example 1.4. Presets 1.5. Selecting and Generating the Design Example 1.6. Design Example with RTL State Machine Control Unit 1.7. Design Example with NIOS Control Unit 1.8. JESD204B Intel® FPGA IP Design Example User Guide Document Archives 1.9. Document Revision History for the JESD204B Intel® FPGA IP Design Example User Guide
1.1. JESD204B Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Compiling and Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Procedure 1.1.2.2. Design Example Parameters
1.1.3. Compiling and Simulating the Design x
1.1.3.1. Procedure
1.6. Design Example with RTL State Machine Control Unit x
1.6.1. Design Example Components 1.6.2. System Parameters 1.6.3. System Interface Signals 1.6.4. Example Feature: Dynamic Reconfiguration 1.6.5. Generating and Simulating the Design Example 1.6.6. Generating the Design Example For Compilation 1.6.7. Compiling the JESD204B IP Core Design Example
1.6.1. Design Example Components x
1.6.1.1. PLL 1.6.1.2. PLL Reconfiguration 1.6.1.3. Transceiver Reconfiguration Controller 1.6.1.4. Transceiver Reset Controller 1.6.1.5. Pattern Generator 1.6.1.6. Pattern Checker 1.6.1.7. Transport Layer 1.6.1.8. Serial Port Interface (SPI) 1.6.1.9. Control Unit
1.6.1.5. Pattern Generator x
1.6.1.5.1. Parallel PRBS Generator 1.6.1.5.2. Alternate Checkerboard Generator 1.6.1.5.3. Ramp Wave Generator
1.6.1.6. Pattern Checker x
1.6.1.6.1. Parallel PRBS Checker 1.6.1.6.2. Alternate Checkerboard Checker 1.6.1.6.3. Ramp Wave Checker
1.6.1.7. Transport Layer x
1.6.1.7.1. Supported System Configuration 1.6.1.7.2. Data Bit and Content Mapping Scheme 1.6.1.7.3. TX Path 1.6.1.7.4. RX Path
1.6.1.9. Control Unit x
1.6.1.9.1. Memory Block (ROM) 1.6.1.9.2. Finite State Machine (FSM)
1.6.2. System Parameters x
1.6.2.1. Run-Time Reconfiguration
1.6.4. Example Feature: Dynamic Reconfiguration x
1.6.4.1. Dynamic Reconfiguration Operation 1.6.4.2. MIF ROM
1.6.5. Generating and Simulating the Design Example x
1.6.5.1. Generating the Design Example Simulation Model 1.6.5.2. Simulating the JESD204B IP Core Design Example
1.7. Design Example with NIOS Control Unit x
1.7.1. Design Example Components 1.7.2. System Clocking 1.7.3. Nios II Processor Design Example Files 1.7.4. Nios II Processor Design Example System Parameters 1.7.5. Nios II Processor Design Example System Interface Signals 1.7.6. Compiling the Design Example for Synthesis 1.7.7. Implementing the Design on the Development Kit 1.7.8. Running the Software Control Flow 1.7.9. Customizing the Design Example
1.7.1. Design Example Components x
1.7.1.1. Platform Designer (Standard) System Component 1.7.1.2. Transport Layer 1.7.1.3. Test Pattern Generator 1.7.1.4. Test Pattern Checker
1.7.1.1. Platform Designer (Standard) System Component x
1.7.1.1.1. JESD204B Subsystem in Platform Designer (Standard) JESD204B IP Core Reset Sequencer Transceiver PHY Reset Controller ATX PLL Avalon-MM Bridge JESD204B Subsystem Address Map 1.7.1.1.2. Nios II Subsystem in Platform Designer (Standard) 1.7.1.1.3. Core PLL 1.7.1.1.4. PLL Reconfiguration Controller 1.7.1.1.5. SPI Master
1.7.7. Implementing the Design on the Development Kit x
1.7.7.1. Pin Assignments 1.7.7.2. Hardware Setup 1.7.7.3. Programming the Device
1.7.8. Running the Software Control Flow x
1.7.8.1. Executing the Software C Code 1.7.8.2. Software Parameters 1.7.8.3. Software Interrupt Service Routines (ISR) 1.7.8.4. Software Functions Description
1.7.8.4. Software Functions Description x
1.7.8.4.1. Functions in main.c Source File 1.7.8.4.2. Custom Peripheral Access Macros in macros.c Source File
1.7.9. Customizing the Design Example x
1.7.9.1. Modifying the JESD204B IP Core Parameters Post-Generation 1.7.9.2. Changing the Data Rate or Reference Clock Frequency 1.7.9.3. Implementing a Multi-Link Design
1.7.9.3. Implementing a Multi-Link Design x
1.7.9.3.1. Editing the Platform Designer (Standard) Project 1.7.9.3.2. Editing the Top Level HDL File 1.7.9.3.3. Editing the Software C Code
1. JESD204B Intel® FPGA IP Design Example User Guide

1.7.1.1.1. JESD204B Subsystem in Platform Designer (Standard)

The JESD204B subsystem Platform Designer (Standard) project, jesd204b_subsystem.qsys, instantiates the following modules:

  • JESD204B IP core (altera_jesd204) configured in duplex, non-bonded mode (with TX and RX datapaths)
  • Reset sequencer (altera_reset_sequencer)
  • Transceiver PHY reset controller (altera_xcvr_reset_control)
  • ATX PLL (altera_xcvr_atx_pll_a10)
  • Avalon-MM bridge (altera_avalon_mm_bridge)

The grouping of modules into a single Platform Designer (Standard) subsystem project facilitates easy implementation of multi-link capabilities. For every link that you implement, a jesd204b_subsystem.qsys project is instantiated in the top level Platform Designer (Standard) project and assigned an address as described in the Address Map section of the Platform Designer (Standard) System section. Each link can be reset and dynamically reconfigured independently.

JESD204B IP Core

The generated example design is a self-contained system with its own JESD204B IP core. This IP core is separate from the IP core that is generated from the IP tab. The example design JESD204B IP core is configured in duplex mode (with TX and RX data paths) and has the IP parameter settings as set when you generate the example design. The JESD204B IP base core and PHY layer connect to the Nios II processor via the Avalon-MM interconnect. There are three separate Avalon-MM ports for the JESD204B IP core:
  • Base core TX data path – For dynamic reconfiguration of the TX CSR parameters
  • Base core RX data path – For dynamic reconfiguration of the RX CSR parameters
  • PHY layer – For dynamic reconfiguration of transceiver PHY CSR (including data rate reconfiguration)

The Nios II processor writes to the JESD204B IP core CSR during a dynamic reconfiguration operation. By default, the software does not contain any dynamic reconfiguration features but you can use the Platform Designer (Standard) system to implement such feature in the software.

Reset Sequencer

The reset sequencer is a standard Platform Designer (Standard) component in the IP Catalog standard library. The reset sequencer generates the following system resets to reset various modules in the system:

  • Core PLL reset—resets the core PLL
  • Transceiver reset—resets the JESD204B IP core PHY module
  • TX/RX JESD204B IP core CSR reset—resets the TX/RX JESD204B IP core CSRs
  • TX/RX link reset—resets the TX/RX JESD204B IP core base module and transport layer
  • TX/RX frame reset—resets the TX/RX transport layer, upstream and downstream modules

The reset sequencer has hard and soft reset options. The hard reset port connects to the global_rst_n input pin in the top level design. The Nios II processor executes a soft reset by issuing the reset command to the Avalon-MM interface of the reset sequencer. When you assert a hard reset or issue the relevant reset command via the Nios II processor, the reset sequencer cycles through all the various module resets based on a pre-set sequence. The figure below illustrates the sequence and also shows how the reset sequencer output ports correspond to the modules that are being reset.

Figure 27. Reset Sequence


Transceiver PHY Reset Controller

The transceiver PHY reset controller is a standard Platform Designer (Standard) component in the IP Catalog standard library. This module takes the transceiver PHY reset output from the reset sequencer and generates the proper analog and digital reset sequencing for the transceiver PHY module.

ATX PLL

The ATX PLL is a standard Platform Designer (Standard) component in the IP Catalog standard library. This module supplies a low-jitter serial clock to the Arria 10 transceiver PHY module. The reference clock input to the ATX PLL is the device_clk. The ATX PLL has an Avalon-MM interface that connects to the Nios II processor via the Avalon-MM interconnect and can receive configuration instructions from the Nios II processor. By default, the software does not contain any dynamic reconfiguration features but you can use the Platform Designer (Standard) system to implement such feature in the software.

Avalon-MM Bridge

All the Avalon-MM submodules in the JESD204B subsystem are connected via Avalon-MM interconnect to a single Avalon-MM bridge. This bridge is the single interface for Avalon-MM communications into and out of the subsystem.

JESD204B Subsystem Address Map

You can access the address map of the submodules in the JESD204B subsystem by clicking on the Address Map tab in the Platform Designer (Standard) window.

Table 35.  JESD204B Subsystem Address MapThis table lists the memory allocation address map.

Avalon-MM Peripheral

Address Map

JESD204B IP core transceiver reconfiguration interface

0x0000 – 0x3FFF

ATX PLL (up to 4 modules per link)

0x8000 – 0x8FFF (Module 0)

0x9000 – 0x9FFF (Module 1)

0xA000 – 0xAFFF (Module 2)

0xB000 – 0xBFFF (Module 3)

JESD204B IP core CSR – TX

0xC000 – 0xC3FF

JESD204B IP core CSR – RX

0xD000 – 0xD3FF

Reset sequencer

0xE000 – 0xE0FF

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