JESD204B Intel® FPGA IP Design Example User Guide: Quartus® Prime Standard Edition

ID 683094
Date 7/19/2024
Public
Document Table of Contents

1.6.5.1. Generating the Design Example Simulation Model

After generating the IP core, generate the design example simulation testbench using the script (gen_ed_sim_verilog.tcl or gen_ed_sim_vhdl) located in the <example_design_directory>/ed_sim directory.

Note: For more information about the JESD204B design example testbench, refer to the README_DESIGN_EXAMPLE.txt file located in the <example_design_directory>/ed_sim folder.

To run the Tcl script using the Quartus® Prime software, follow these steps:

  1. Launch the Quartus® Prime software.
  2. On the View menu, click Utility Windows and select Tcl Console.
  3. In the Tcl Console, type cd <example_design_directory>/ed_sim to go to the specified directory.
  4. Type source gen_ed_sim_verilog.tcl (Verilog) or source gen_ed_sim_vhdl.tcl (VHDL) to generate the simulation files.

To run the Tcl script using the command line, follow these steps:

  1. Obtain the Quartus® Prime software resource.
  2. Type cd <example_design_directory>/ed_sim to go to the specified directory.
  3. Type quartus_sh -t gen_ed_sim_verilog.tcl (Verilog) or quartus_sh -t gen_ed_sim_vhdl.tcl (VHDL) to generate the simulation files.