JESD204B Intel® FPGA IP Design Example User Guide: Quartus® Prime Standard Edition
ID
683094
Date
7/19/2024
Public
1.1. JESD204B Design Example Quick Start Guide
1.2. Supported Configurations
1.3. Generic Design Example
1.4. Presets
1.5. Selecting and Generating the Design Example
1.6. Design Example with RTL State Machine Control Unit
1.7. JESD204B Intel® FPGA IP Design Example User Guide Document Archives
1.8. Document Revision History for the JESD204B Intel® FPGA IP Design Example User Guide
1.6.1.4. Transceiver Reset Controller
The transceiver reset controller uses the Altera's Transceiver PHY Reset Controller IP Core to ensure a reliable initialization of the transceiver. The reset controller has separate reset controls per channel to handle synchronization of reset inputs, hysteresis of PLL locked status, and automatic or manual reset recovery mode.
In this design example, the reset controller targets both the TX and RX channels. The TX PLL , TX Channel , and RX Channel parameters are programmable to accommodate single and multiple (2) JESD204B links.