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1. Intel® MAX® 10 FPGA Configuration Overview
2. Intel® MAX® 10 FPGA Configuration Schemes and Features
3. Intel® MAX® 10 FPGA Configuration Design Guidelines
4. Intel® MAX® 10 FPGA Configuration IP Core Implementation Guides
5. Dual Configuration Intel® FPGA IP Core References
6. Unique Chip ID Intel® FPGA IP Core References
7. Document Revision History for the Intel® MAX® 10 FPGA Configuration User Guide
3.1. Dual-Purpose Configuration Pins
3.2. Configuring Intel® MAX® 10 Devices using JTAG Configuration
3.3. Configuring Intel® MAX® 10 Devices using Internal Configuration
3.4. Implementing ISP Clamp in Intel® Quartus® Prime Software
3.5. Accessing Remote System Upgrade through User Logic
3.6. Error Detection
3.7. Enabling Data Compression
3.8. AES Encryption
3.9. Intel® MAX® 10 JTAG Secure Design Example
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2.1.1.1. JTAG Pins
Pin | Function | Description |
---|---|---|
TDI | Serial input pin for:
|
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TDO | Serial output pin for:
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TMS | Input pin that provides the control signal to determine the transitions of the TAP controller state machine. |
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TCK | Clock input to the BST circuitry. | — |
All the JTAG pins are powered by the VCCIO 1B. In JTAG mode, the I/O pins support the LVTTL/LVCMOS 3.3-1.5V standards.
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