Intel® MAX® 10 FPGA Configuration User Guide

ID 683865
Date 3/27/2023
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3.9.2. JTAG WYSIWYG Atom for JTAG Control Block Access Using Internal JTAG Interface

The following example shows how the input and output ports of a JTAG WYSIWYG atom are defined in the Intel® MAX® 10 device.

fiftyfivenm_jtag <name>
Table 34.  Port Description
Ports Input/Output Functions
<name> Identifier for the Intel® MAX® 10 JTAG WYSIWYG atom and represents any identifier name that is legal for the given description language, such as Verilog HDL, VHDL, and AHDL.
.corectl() Input Active high input to the JTAG control block to enable the internal JTAG access from core interface. When the FPGA enters user mode after configuration, this port is low by default. Pulling this port to logic high will enable the internal JTAG interface (with external JTAG interface disabled at the same time) and pulling this port to logic low will disable the internal JTAG interface (with external JTAG interface enabled at the same time).
.tckcore() Input Core tck signal
.tdicore() Input Core tdi signal
.tmscore() Input Core tms signal
.tdocore() Output Core tdo signal
.tck() Input Pin tck signal
.tdi() Input Pin tdi signal
.tms() Input Pin tms signal
.tdo() Output Pin tdo signal
.clkdruser() Input/Output These ports are not used for enabling the JTAG Secure mode using the internal JTAG interface, you can leave them unconnected.