Intel® MAX® 10 FPGA Configuration User Guide

ID 683865
Date 3/27/2023
Document Table of Contents Real-Time ISP

In a normal ISP operation, to update the internal flash with a new design image, the device exits from user mode and all I/O pins remain tri-stated. After the device completes programing the new design image, it resets and enters user mode.

The real-time ISP feature updates the internal flash with a new design image while operating in user mode. During the internal flash programming, the device continues to operate using the existing design. After the new design image programming process completes, the device will not reset. The new design image update only takes effect in the next reconfiguration cycle.

Did you find the information on this page useful?

Characters remaining:

Feedback Message