Intel® MAX® 10 FPGA Configuration User Guide

ID 683865
Date 3/27/2023
Document Table of Contents

3.9. Intel® MAX® 10 JTAG Secure Design Example

This design example demonstrates the instantiation of the JTAG WYSIWYG atom and the example of user logic implementation in the Intel® Quartus® Prime software to execute the LOCK and UNLOCK JTAG instructions. This design example is targeted for Intel® MAX® 10 devices with the JTAG Secure Mode enabled.

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