1. MAX® 10 FPGA Configuration Overview
2. MAX® 10 FPGA Configuration Schemes and Features
3. MAX® 10 FPGA Configuration Design Guidelines
4. MAX® 10 FPGA Configuration IP Core Implementation Guides
5. Dual Configuration Intel® FPGA IP Core References
6. Unique Chip ID Intel® FPGA IP Core References
7. Document Revision History for the MAX® 10 FPGA Configuration User Guide
3.1. Dual-Purpose Configuration Pins
3.2. Configuring MAX® 10 Devices using JTAG Configuration
3.3. Configuring MAX® 10 Devices using Internal Configuration
3.4. Implementing ISP Clamp in Quartus® Prime Software
3.5. Accessing Remote System Upgrade through User Logic
3.6. Error Detection
3.7. Enabling Data Compression
3.8. AES Encryption
3.9. MAX® 10 JTAG Secure Design Example
4.2.1. Instantiating the Dual Configuration Intel® FPGA IP Core
To instantiate the Dual Configuration Intel® FPGA IP Core, follow these steps:
- On the Tools menu of the Quartus® Prime software, click IP Catalog.
- Under the Library category, expand the Basic Functions and Configuration Programming.
- Select Dual Configuration Intel® FPGA IP and after clicking Add, the IP Parameter Editor appears.
- In the New IP Instance dialog box:
- Set the top-level name of your IP.
- Select the Device family.
- Select the Device
- Click OK.