1. MAX® 10 FPGA Configuration Overview
2. MAX® 10 FPGA Configuration Schemes and Features
3. MAX® 10 FPGA Configuration Design Guidelines
4. MAX® 10 FPGA Configuration IP Core Implementation Guides
5. Dual Configuration Intel® FPGA IP Core References
6. Unique Chip ID Intel® FPGA IP Core References
7. Document Revision History for the MAX® 10 FPGA Configuration User Guide
3.1. Dual-Purpose Configuration Pins
3.2. Configuring MAX® 10 Devices using JTAG Configuration
3.3. Configuring MAX® 10 Devices using Internal Configuration
3.4. Implementing ISP Clamp in Quartus® Prime Software
3.5. Accessing Remote System Upgrade through User Logic
3.6. Error Detection
3.7. Enabling Data Compression
3.8. AES Encryption
3.9. MAX® 10 JTAG Secure Design Example
2.2.3.1. Configuration Error Detection
In configuration mode, a frame-based CRC is stored in the configuration data and contains the CRC value for each data frame.
During configuration, the MAX® 10 device calculates the CRC value based on the frame of data that is received and compares it against the frame CRC value in the data stream. Configuration continues until the device detects an error or when all the values are calculated.
For MAX® 10 devices, the CRC is computed by the Quartus® Prime software and downloaded into the device as part of the configuration bit stream. These devices store the CRC in the 32-bit storage register at the end of the configuration mode.