1. MAX® 10 FPGA Configuration Overview
2. MAX® 10 FPGA Configuration Schemes and Features
3. MAX® 10 FPGA Configuration Design Guidelines
4. MAX® 10 FPGA Configuration IP Core Implementation Guides
5. Dual Configuration Intel® FPGA IP Core References
6. Unique Chip ID Intel® FPGA IP Core References
7. Document Revision History for the MAX® 10 FPGA Configuration User Guide
3.1. Dual-Purpose Configuration Pins
3.2. Configuring MAX® 10 Devices using JTAG Configuration
3.3. Configuring MAX® 10 Devices using Internal Configuration
3.4. Implementing ISP Clamp in Quartus® Prime Software
3.5. Accessing Remote System Upgrade through User Logic
3.6. Error Detection
3.7. Enabling Data Compression
3.8. AES Encryption
3.9. MAX® 10 JTAG Secure Design Example
3.8. AES Encryption
Security Notice: The MAX® 10 devices use 128-bit encryption keys. For higher levels of security, Altera recommends that you select devices using longer key lengths such as Stratix® 10 or Agilex™ 7 devices, which use 256-bit encryption keys.
This section covers detailed guidelines on applying AES Encryption for design security.
There are two main steps in applying design security in MAX® 10 devices. First is to generate the encryption key programming (.ekp) file and second is to program the .ekp file into the device.
The .ekp file has other different formats, depending on the hardware and system used for programming. There are three file formats supported by the Quartus® Prime software:
- JAM Byte Code (.jbc) file
- JAM™ Standard Test and Programming Language (STAPL) Format (.jam) file
- Serial Vector Format (.svf) file
Only the .ekp file type generated automatically from the Quartus® Prime software. You must create the .jbc, .jam, and .svf files using the Quartus® Prime software if these files are required in the key programming.
Note: Altera recommends that you keep the .ekp file confidential.