Intel® MAX® 10 FPGA Configuration User Guide

ID 683865
Date 3/27/2023
Document Table of Contents
Give Feedback In-System Programming

You can program the internal flash including the CFM of Intel® MAX® 10 devices with ISP through industry standard IEEE 1149.1 JTAG interface. ISP offers the capability to program, erase, and verify the CFM. The JTAG circuitry and ISP instructions for Intel® MAX® 10 devices are compliant to the IEEE-1532-2002 programming specification.

During ISP, the Intel® MAX® 10 receives the IEEE Std. 1532 instructions, addresses, and data through the TDI input pin. Data is shifted out through the TDO output pin and compared with the expected data.

The following are the generic flow of an ISP operation:

  1. Check ID—the JTAG ID is checked before any program or verify process. The time required to read this JTAG ID is relatively small compared to the overall programming time.
  2. Enter ISP—ensures the I/O pins transition smoothly from user mode to the ISP mode.
  3. Sector Erase—shifting in the address and instruction to erase the device and applying erase pulses.
  4. Program—shifting in the address, data, and program instructions and generating the program pulse to program the flash cells. This process is repeated for each address in the internal flash sector.
  5. Verify—shifting in addresses, applying the verify instruction to generate the read pulse, and shifting out the data for comparison. This process is repeated for each internal flash address.
  6. Exit ISP—ensures that the I/O pins transition smoothly from the ISP mode to the user mode.

You can also use the Intel® Quartus® Prime Programmer to program the CFM.