Intel® MAX® 10 FPGA Configuration User Guide

ID 683865
Date 3/27/2023
Public
Document Table of Contents

2.2.3.2.2. CHANGE_EDREG JTAG Instruction

Table 20.   CHANGE_EDREG JTAG Instruction Description
JTAG Instruction Instruction Code Description
CHANGE_EDREG 00 0001 0101 This instruction connects the 32-bit CRC storage register between TDI and TDO. Any precomputed CRC is loaded into the CRC storage register to test the operation of the error detection CRC circuitry at the CRC_ERROR pin.

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