Intel® MAX® 10 FPGA Configuration User Guide

ID 683865
Date 3/27/2023
Document Table of Contents User Watchdog Timer

The user watchdog timer prevents a faulty application configuration from stalling the device indefinitely. You can use the timer to detect functional errors when an application configuration is successfully loaded into the device.

The counter is 29 bits wide and has a maximum count value of 229. When specifying the user watchdog timer value, specify only the most significant 12 bits. The granularity of the timer setting is 217 cycles. The cycle time is based on the frequency of the user watchdog timer internal oscillator. Depending on the counter and the internal oscillator of the device, you can set the cycle time from 9 ms to 244 s.

Figure 5. Watchdog Timer Formula for Intel® MAX® 10 Devices

The timer begins counting as soon as the application configuration enters user mode. When the timer expires, the remote system upgrade circuitry generates a time-out signal, updates the status register, and triggers the loading of the revert configuration image. To reset the timer and ensure that the application configuration is valid, pulse the RU_NRSTIMER continuously for a minimum of 250 ns per reset pulse.

When you enable the watchdog timer, the setting applies to all images, all images should contain the soft logic configuration to reset the timer. Application configuration will reset the control block registers.

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