Intel® MAX® 10 FPGA Configuration User Guide

ID 683865
Date 3/27/2023
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2.2.3. SEU Mitigation and Configuration Error Detection

The dedicated circuitry built in Intel® MAX® 10 devices consists of an error detection cyclic redundancy check (EDCRC) feature. You can use this feature to mitigate single-event upset (SEU) or soft errors.

The hardened on-chip EDCRC circuitry allows you to perform the following operations without any impact on the fitting of the device:

  • Auto-detection of cyclic redundancy check (CRC) errors during configuration.
  • Identification of SEU in user mode with the optional CRC error detection.
  • Testing of error detection by error detection verification through the JTAG interface.