Intel® MAX® 10 FPGA Configuration User Guide

ID 683865
Date 3/27/2023
Document Table of Contents

3.1.1. Guidelines: Dual-Purpose Configuration Pin

To use configuration pins as user I/O pins in user mode, you have to adhere to the following guidelines.
Table 26.  Dual-Purpose Configuration Pin Guidelines for Intel® MAX® 10 Devices
Guidelines Pins
Configuration pins during initialization:
  • Tri-state the external I/O driver and drive an external pull-up resistor 13 or
  • Use the external I/O driver to drive the pins to the state same as the external weak pull-up resistor
JTAG pins:
  • If you intend to switch back and forth between user I/O pins and JTAG pin functions using the JTAGEN pin, all JTAG pins must be assigned as single-ended I/O pins or voltage-referenced I/O pins. Schmitt trigger input is the recommended input buffer.
  • JTAG pins cannot perform as JTAG pins in user mode if you assign any of the JTAG pin as a differential I/O pin.
  • You must use the JTAG pins as dedicated pins and not as user I/O pins during JTAG programming.
  • Do not toggle JTAG pin during the initialization stage.
  • Put the test access port (TAP) controller in reset state by driving the TDI and TMS pins high and toggle the TCK pin for at least 5 clock cycles before the initialization.
  • The Signal Tap logic analyzer IP, JTAG-to- Avalon® master bridge IP, and other JTAG-related IPs cannot be used if you enable the JTAG pin sharing feature in your design.
  • TDO
  • TMS
  • TCK
  • TDI
Attention: Assign all JTAG pins as single-ended I/O pins or voltage-referenced I/O pins if you enable JTAG pin sharing feature.
13 If you intend to remove the external weak pull-up resistor, Intel recommends that you remove it after the device enters user mode.