1. Intel® MAX® 10 FPGA Configuration Overview 2. Intel® MAX® 10 FPGA Configuration Schemes and Features 3. Intel® MAX® 10 FPGA Configuration Design Guidelines 4. Intel® MAX® 10 FPGA Configuration IP Core Implementation Guides 5. Dual Configuration Intel® FPGA IP Core References 6. Unique Chip ID Intel® FPGA IP Core References 7. Document Revision History for the Intel® MAX® 10 FPGA Configuration User Guide
3.1. Dual-Purpose Configuration Pins 3.2. Configuring Intel® MAX® 10 Devices using JTAG Configuration 3.3. Configuring Intel® MAX® 10 Devices using Internal Configuration 3.4. Implementing ISP Clamp in Intel® Quartus® Prime Software 3.5. Accessing Remote System Upgrade through User Logic 3.6. Error Detection 3.7. Enabling Data Compression 3.8. AES Encryption 3.9. Intel® MAX® 10 JTAG Secure Design Example
3.6.3. Accessing Error Detection Block Through User Logic
The error detection circuit stores the computed 32-bit CRC signature in a 32-bit register. The user logic from the core reads out this signature. The fiftyfivenm_crcblock primitive is a WYSIWYG component used to establish the interface from the user logic to the error detection circuit. The fiftyfivenm_crcblock primitive atom contains the input and output ports that must be included in the atom. To access the logic array,you must insert the fiftyfivenm_crcblock WYSIWYG atom into your design. The recommended clock frequency of .clk port is to follow the clock frequency of EDCRC block.
Figure 15. Error Detection Block Diagram with Interfaces for Intel® MAX® 10 Devices
The following example shows how the input and output ports of a WYSIWYG atom are defined in the Intel® MAX® 10 device.
fiftyfivenm_crcblock <name> ( .clk(<ED_CLK clock source>), .shiftnld(<ED_SHIFTNLD source>), .ldsrc (<LDSRC source>), .crcerror(<CRCERROR_CORE out destination>), .regout(<output destination>) ); defparam <crcblock_name>.oscillator_divider = <internal oscillator division (1 to 256)>;
|<crcblock_name>||—||Unique identifier for the CRC block and represents any identifier name that is legal for the given description language such as Verilog HDL, VHDL, AHDL. This field is required.|
|.clk(<clock source>||Input||This signal designates the clock input of this cell. All operations of this cell are with respect to the rising edge of the clock. Whether it is the loading of the data into the cell or data out of the cell, it always occurs on the rising edge. This port is required.|
|.shiftnld (<shiftnld source>)||Input||This signal is an input into the error detection block. If shiftnld=1, the data is shifted from the internal shift register to the regout at each rising edge of clk. If shiftnld=0, the shift register parallel loads either the pre-calculated CRC value or the update register contents depending on the ldsrc port input. This port is required.|
|.ldsrc (<ldsrc source>)||Input||This signal is an input into the error detection block. If ldsrc=0, the pre-computed CRC register is selected for loading into the 32-bit shift register at the rising edge of clk when shiftnld=0. Ifldsrc=1, the signature register (result of the CRC calculation) is selected for loading into the shift register at the rising edge of clk when shiftnld=0. This port is ignored when shiftnld=1. This port is required.|
|.crcerror (<crcerror out destination>)||Output||This signal is the output of the cell that is synchronized to the internal oscillator of the device (100-MHz or 80-MHz internal oscillator) and not to the clk port. It asserts automatically high if the error block detects that a SRAM bit has flipped and the internal CRC computation has shown a difference with respect to the pre-computed value. This signal must be connected either to an output pin or a bidirectional pin. If it is connected to an output pin, you can only monitor the CRC_ERROR pin (the core cannot access this output). If the CRC_ERROR signal is used by core logic to read error detection logic, this signal must be connected to a BIDIR pin. The signal is fed to the core indirectly by feeding a BIDIR pin that has its oe port connected to VCC.|
|.regout (<output destination>)||Output||This signal is the output of the error detection shift register synchronized to the clk port, to be read by core logic. It shifts one bit at each cycle. User should clock the clk signal 31 cycles to read out the 32 bits of the shift register. The values at the .regout port are an inversion of the actual values.|