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1. Intel® MAX® 10 FPGA Configuration Overview
2. Intel® MAX® 10 FPGA Configuration Schemes and Features
3. Intel® MAX® 10 FPGA Configuration Design Guidelines
4. Intel® MAX® 10 FPGA Configuration IP Core Implementation Guides
5. Dual Configuration Intel® FPGA IP Core References
6. Unique Chip ID Intel® FPGA IP Core References
7. Document Revision History for the Intel® MAX® 10 FPGA Configuration User Guide
3.1. Dual-Purpose Configuration Pins
3.2. Configuring Intel® MAX® 10 Devices using JTAG Configuration
3.3. Configuring Intel® MAX® 10 Devices using Internal Configuration
3.4. Implementing ISP Clamp in Intel® Quartus® Prime Software
3.5. Accessing Remote System Upgrade through User Logic
3.6. Error Detection
3.7. Enabling Data Compression
3.8. AES Encryption
3.9. Intel® MAX® 10 JTAG Secure Design Example
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2.2.2.3. JTAG Secure Mode
In JTAG Secure mode, the device only allows mandatory IEEE 1149.1 JTAG instructions to be exercised.
You can enable the JTAG secure when generating the .pof in the Convert Programming Files. To exit JTAG secure mode, issue the UNLOCK JTAG instruction. The LOCK JTAG instruction puts the device in the JTAG secure mode again. The LOCK and UNLOCK JTAG instructions can only be issued through the JTAG core access. Refer to JTAG Instruction Availability for list of available instructions.