1. MAX® 10 FPGA Configuration Overview
2. MAX® 10 FPGA Configuration Schemes and Features
3. MAX® 10 FPGA Configuration Design Guidelines
4. MAX® 10 FPGA Configuration IP Core Implementation Guides
5. Dual Configuration Intel® FPGA IP Core References
6. Unique Chip ID Intel® FPGA IP Core References
7. Document Revision History for the MAX® 10 FPGA Configuration User Guide
3.1. Dual-Purpose Configuration Pins
3.2. Configuring MAX® 10 Devices using JTAG Configuration
3.3. Configuring MAX® 10 Devices using Internal Configuration
3.4. Implementing ISP Clamp in Quartus® Prime Software
3.5. Accessing Remote System Upgrade through User Logic
3.6. Error Detection
3.7. Enabling Data Compression
3.8. AES Encryption
3.9. MAX® 10 JTAG Secure Design Example
2.2.1.2.1. Remote System Upgrade Circuitry Signals
Core Signal Name | Logical Signal Name | Input/Output | Description |
---|---|---|---|
RU_DIN | regin | Input | Use this signal to write data to the shift register on the rising edge of RU_CLK. To load data to the shift register, assert RU_SHIFTnLD. |
RU_DOUT | regout | Output | Use this signal to get output data from the shift register. Data is clocked out on each rising edge of RU_CLK if RU_SHIFTnLD is asserted. |
RU_nRSTIMER | rsttimer | Input |
|
RU_nCONFIG | rconfig | Input | Use this signal to reconfigure the device. Driving this signal low triggers the device to reconfigure if you enable the remote system upgrade feature. |
RU_CLK | clk | Input | The clock to the remote system upgrade circuitry. All registers in this clock domain are enabled in user mode if you enable the remote system upgrade. Shift register and input register are positive edge flip-flops. |
RU_SHIFTnLD | shiftnld | Input | Control signals that determine the mode of remote system upgrade circuitry.
|
RU_CAPTnUPDT | captnupdt | Input |
Related Information