Intel® MAX® 10 FPGA Configuration User Guide

ID 683865
Date 3/27/2023
Document Table of Contents
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6.1. Unique Chip ID Intel® FPGA IP Core Ports

Table 38.  Unique Chip ID Intel® FPGA IP Core Ports
Port Input/Output Width (Bits) Description
clkin Input 1
  • Feeds clock signal to the unique chip ID block. The maximum supported frequency is 100 MHz.
  • When you provide a clock signal, the IP core reads the value of the unique chip ID and sends the value to the chip_id output port.
reset Input 1
  • Resets the IP core when you assert the reset signal to high for at least one clock cycle.
  • The chip_id [63:0]output port holds the value of the unique chip ID until you reconfigure the device or reset the IP core.
data_valid Output 1
  • Indicates that the unique chip ID is ready for retrieval. If the signal is low, the IP core is in initial state or in progress to load data from a fuse ID.
  • After the IP core asserts the signal, the data is ready for retrieval at the chip_id[63..0] output port.
chip_id Output 64
  • Indicates the unique chip ID according to its respective fuse ID location. The data is only valid after the IP core asserts the data_valid signal.
  • The value at power-up resets to 0.