Intel® MAX® 10 FPGA Configuration User Guide

ID 683865
Date 3/27/2023
Document Table of Contents
Give Feedback ISP and Real-Time ISP Instructions

Table 5.  ISP and Real-Time ISP Instructions for Intel® MAX® 10 Devices
Instruction Instruction Code Description
CONFIG_IO 00 0000 1101
  • Allows I/O reconfiguration through JTAG ports using the IOCSR for JTAG testing. This is executed after or during configurations.
  • nSTATUS pin must go high before you can issue the CONFIG_IO instruction.
PULSE_NCONFIG 00 0000 0001 Emulates pulsing the nCONFIG pin low to trigger reconfiguration even though the physical pin is unaffected.
ISC_ENABLE_HIZ 2 10 1100 1100
  • Puts the device in ISP mode, tri-states all I/O pins, and drives all core drivers, logic, and registers.
  • Device remains in the ISP mode until the ISC_DISABLE instruction is loaded and updated.
  • The ISC_ENABLE instruction is a mandatory instruction. This requirement is met by the ISC_ENABLE_CLAMP or ISC_ENABLE_HIZ instruction.
ISC_ENABLE_CLAMP 2 10 0011 0011
  • Puts the device in ISP mode and forces all I/O pins to follow the contents of the JTAG boundary-scan register.
  • When this instruction is activated, all core drivers, logics, and registers are frozen. The I/O pins remain clamped until the device exits ISP mode successfully.
ISC_DISABLE 10 0000 0001
  • Brings the device out of ISP mode.
  • Successful completion of the ISC_DISABLE instruction happens immediately after waiting 200 µs in the Run-Test/Idle state.
ISC_PROGRAM 3 10 1111 0100 Sets the device up for in-system programming. Programming occurs in the run-test or idle state.
ISC_NOOP 3 10 0001 0000
  • Sets the device to a no-operation mode without leaving the ISP mode and targets the ISC_Default register.
  • Use when:
    • two or more ISP-compliant devices are being accessed in ISP mode and;
    • a subset of the devices perform some instructions while other more complex devices are completing extra steps in a given process.
ISC_ADDRESS_SHIFT 3 10 0000 0011 Sets the device up to load the flash address. It targets the ISC_Address register, which is the flash address register.
ISC_ERASE 3 10 1111 0010
  • Sets the device up to erase the internal flash.
  • Issue after ISC_ADDRESS_SHIFT instruction.
ISC_READ 3 10 0000 0101
  • Sets the device up for verifying the internal flash under normal user bias conditions.
  • The ISC_READ instruction supports explicit addressing and auto-increment, also known as the Burst mode.
BGP_ENABLE 01 1001 1001
  • Sets the device to the real-time ISP mode.
  • Allows access to the internal flash configuration sector while the device is still in user mode.
BGP_DISABLE 01 0110 0110
  • Brings the device out of the real-time ISP mode.
  • The device has to exit the real-time ISP mode using the BGP_DISABLE instruction after it is interrupted by reconfiguration.
Do not use unsupported JTAG instructions. Unsupported JTAG instructions put the device into an unknown state and requires a power cycle to recover the operation.
2 Do not issue the ISC_ENABLE_HIZ and ISC_ENABLE_CLAMP instructions from the core logic.
3 All ISP and real-time ISP instructions are disabled when the device is not in the ISP or real-time ISP mode, except for the enabling and disabling instructions.