Visible to Intel only — GUID: igc1481130057253
Ixiasoft
Visible to Intel only — GUID: igc1481130057253
Ixiasoft
16.4.3.2.1.2. Single Block Data
If the ctype register is set for a 1‑bit, 4‑bit, or 8‑bit data transfer, the data is transmitted on 1, 4, or 8 data lines, respectively, and CRC‑16 is separately generated and transmitted for 1, 4, or 8 data lines, respectively.†
After a single data block is transmitted, the data transmit state machine receives the CRC status from the card and signals a data transfer to the BIU. This happens when the dto bit in the rintsts register is set to 1.†
If a negative CRC status is received from the card, the data path signals a data CRC error to the BIU by setting the dcrc bit in the rintsts register.†
Additionally, if the start bit of the CRC status is not received by two clock cycles after the end of the data block, a CRC status start‑bit error (SBE) is signaled to the BIU by setting the sbe bit in the rintsts register.†