Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

A. Booting and Configuration

The Secure Device Manager (SDM) in the FPGA manages the hard processor system (HPS) boot and FPGA configuration of the Intel® Agilex™ SoC device. Both the HPS boot and FPGA configuration comprise a series of stages that always begins with SDM initialization.

After the Intel® Agilex™ SoC device is released from power-on-reset (POR), the SDM manages the initial configuration of the device. All configuration and boot source interfaces are connected to the SDM. The SDM determines and enforces the security level on the device, ensuring the bitstream, which includes the HPS first stage bootloader (FSBL), originate from a trusted source.

You can program the Intel® Agilex™ SoC device to configure the FPGA first and then boot the HPS. Alternatively, you can boot the HPS first and then configure the FPGA core as part of the second-stage boot loader (SSBL) or after the Operating System (OS) boots.

The following documents provide a comprehensive guidance on managing the HPS boot, FPGA configuration and security:

Intel describes configuration schemes from the point-of-view of the FPGA. Intel® Agilex™ devices support active and passive configuration schemes. In active configuration schemes the FPGA acts as the master and the external memory acts as a slave device. In passive configuration schemes an external host acts as the master and controls configuration. The FPGA acts as the slave device. All Intel® Agilex™ configuration schemes support design security, remote system update, and partial reconfiguration. To implement remote system update in passive configuration schemes, an external controller must store and drive the configuration bitstream.

Intel® Agilex™ devices support the following configuration schemes:
  • Avalon® Streaming ( Avalon® -ST)
  • JTAG
  • Configuration via Protocol (CvP)
  • Active Serial (AS) normal and fast modes
  • Secure Digital and Multi Media Card (SD/MMC)

Avalon-ST

The Avalon® -ST configuration scheme is a passive configuration scheme. Avalon® -ST is the fastest configuration scheme for Intel® Agilex™ devices. Avalon® -ST configuration supports x8, x16, and x32 modes. The x16 and x32 bit modes use general-purpose I/Os (GPIOs) for configuration. The x8 bit mode uses dedicated SDM I/O pins.

Note: The AVST_data[15:0], AVST_data[31:0], AVST_clk, and AVST_valid use dual-purpose GPIOs which operate at 1.2 V. You can use these pins as regular I/Os after the device enters user mode.

Avalon® -ST supports backpressure using the AVST_READY and AVST_VALID pins. Because the time to decompress the incoming bitstream varies, backpressure support is necessary to transfer data to the Intel® Agilex™ device. For more information about the Avalon® -ST refer to the Avalon® Interface Specifications.

JTAG

You can configure the Intel® Agilex™ device using the dedicated JTAG pins. The JTAG port provides seamless access to many useful tools and functions. In addition to configuring the Intel® Agilex™ , the JTAG port is used for debugging with Signal Tap or the System Console tools.

The JTAG port has the highest priority and overrides the MSEL pin settings. Consequently, you can configure the Intel® Agilex™ device over JTAG even if the MSEL pin specify a different configuration scheme unless you disabled JTAG for security reasons.

CvP

CvP uses an external PCIe® host device as a Root Port to configure the Intel® Agilex™ device over the PCIe® link. You can specify up to a x16 PCIe® link. Typically, the bitstream compression ratio and the SDM input buffer data rate, not the PCIe® link, limit the configuration data rate. Intel® Agilex™ devices support two CvP modes, CvP init and CvP update.

CvP initialization process includes the following two steps:
  1. CvP configures the FPGA periphery image which includes I/O information and hard IP blocks, including the PCIe® IP. Because the PCIe® IP is in the periphery image, PCIe® link training establishes the PCIe® link of the CvP PCIe® IP before the core fabric configures.
  2. The host device uses the CvP PCIe® link to configure your design in the core fabric.

CvP update mode updates the FPGA core image using the PCIe® link already established from a previous full chip configuration or CvP init configuration. After the Intel® Agilex™ enters user mode, you can use the CvP update mode to reconfigure the FPGA fabric. This mode has the following advantages:

  • Allows reprogramming of the core to run different algorithms.
  • Provides a mechanism for standard updates as a part of a release process.
  • Customizes core processing for different components that are part of a complex system.

    For both CvP Init and CvP Update modes, the maximum data rate depends on the PCIe® generation and number of lanes.

For Intel® Agilex™ SoC devices, CvP is only supported in FPGA configuration first mode.

AS Normal Mode

Active Serial x4 or AS x4 or Quad SPI is an active configuration scheme that supports flash memories capable of three- and four-byte addressing. Upon power up, the SDM boots from a boot ROM which uses three-byte addressing to load the configuration firmware from the Quad SPI flash. After the configuration firmware loads, the Quad SPI flash operates using four-byte addressing for the rest of the configuration process.

AS Fast Mode

The only difference between AS normal mode and fast mode is speed. Use AS fast mode when configuration timing is a concern. Use this mode to meet the 100 ms of power up requirement for PCIe® or for other systems with strict timing requirements.

In AS fast mode, the SDM first powers the external AS x4 flash. The power supply must be able to provide an equally fast ramp up for the Intel® Agilex™ device and the external AS x4 flash devices. Failing to meet this requirement causes the SDM to assume the memory is missing. Consequently, configuration fails.

SD/MMC

SD/MMC is an active configuration scheme. The Intel® Agilex™ SDM can initiate configuration from SD, Secure Digital High Capacity (SDHC*), Secure Digital Extended Capacity (SDXC*), MMC cards, and eMMC devices. The SD/MMC mode is almost identical to AS x4. The advantages of this mode are cost, capacity, availability, portability, and compatibility. Because Intel® Agilex™ devices operate at 1.8 volt an intermediate voltage level shifter may be required to interface with the higher voltage I/Os in SD/MMC devices.