Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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7.3.5.2. FPGA-to-HPS CCU to Memory (Cache Non-Allocate)

The interface from the FPGA to the HPS CCU is ACE-Lite*. These transactions go through the CCU, but can be cached or not cached, based on AxCACHE parameters. Transactions can be privileged or non-privileged depending on memory allocation.

Note: Memory is SDRAM or On-chip RAM (OCRAM).

If your logic issues a Cache Non-Allocate transaction, the CCU maintains coherency but does not allocate in the cache. This is useful when you want to maintain coherency but not thrash the cache.

Reads

  • On cache hits, read data is returned by the cache.
  • On cache misses, read data is returned from main memory and not allocated (stored) in cache.
Table 71.  Read Data Attribute List
ATTRIBUTE VALUE NOTE
ARDOMAIN[1:0] ’b01 Inner Sharable
ARBAR[1:0] ‘b00 Normal access, respecting barriers
ARSNOOP[3:0] ‘b0000 ReadOnce
ARCACHE[3:0] ‘b1011 Write-back No-allocate
AxUSER[7:0] ‘b00000100 0x04 = CCU
AxPROT[2:0] ‘b001 Data access. Secure access. Privileged access.
AxLEN[7:0]
The burst length for:
  • WRAP burst type must be 1, 2, 4, 8 or 16 transfers.
  • INCR burst type is 1 to 256 transfers.
AxSIZE[2:0] The number of bytes in a transfer must be equal to the data bus width
AxBURST[1:0] ‘b01 or ‘b10 Must be INCR(‘b01) or WRAP(‘b10)
AxLOCK[1:0] ‘b00 Must be normal access
AxQOS Do not care

Writes

  • On cache hits, write data is stored in cache.
  • On cache misses, write data is stored to main memory.
Table 72.  Write Data Attribute List
ATTRIBUTE VALUE NOTE
AWDOMAIN[1:0] ’b01 Inner Sharable
AWBAR[1:0] ‘b00 Normal access, respecting barriers
AWSNOOP[2:0] ‘b000 WriteUnique (could be ‘b001 for WriteLineUnique)
AWCACHE[3:0] ‘b0111 Write-back No-allocate
AxUSER[7:0] ‘b00000100 0x04 = CCU
AxPROT[2:0] ‘b001 Data access. Secure access. Privileged access.
AxLEN[7:0]
The burst length for:
  • WRAP burst type must be 1, 2, 4, 8 or 16 transfers.
  • INCR burst type is 1 to 256 transfers.
AxSIZE[2:0] The number of bytes in a transfer must be equal to the data bus width
AxBURST[1:0] ‘b01 or ‘b10 Must be INCR(‘b01) or WRAP(‘b10)
AxLOCK[1:0] ‘b00 Must be normal access
AxQOS Do not care